KMAC/UNMASKED Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	44.010s	4.244ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.780s	93.691us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.910s	59.056us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.160s	500.146us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.950s	149.062us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.680s	252.963us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.910s	59.056us	1	1	100.00
		kmac_csr_aliasing	5.950s	149.062us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.620s	11.527us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.840s	21.862us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	32.089m	80.712ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.845m	26.521ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.534m	64.436ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.260s	2.429ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.930s	431.277us	1	1	100.00
		kmac_test_vectors_sha3_512	13.730s	975.953us	1	1	100.00
		kmac_test_vectors_shake_128	21.755m	91.331ms	1	1	100.00
		kmac_test_vectors_shake_256	23.377m	101.040ms	1	1	100.00
		kmac_test_vectors_kmac	2.540s	59.246us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.530s	38.587us	1	1	100.00
V2	sideload	kmac_sideload	3.741m	9.427ms	1	1	100.00
V2	app	kmac_app	3.193m	6.526ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.507m	14.782ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.004m	15.082ms	1	1	100.00
V2	error	kmac_error	2.636m	5.191ms	1	1	100.00
V2	key_error	kmac_key_error	4.330s	3.514ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.280s	371.695us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.220s	330.544us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.380s	5.777ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	42.580s	58.066ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.760s	152.166us	1	1	100.00
V2	stress_all	kmac_stress_all	48.810s	1.830ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.570s	99.967us	1	1	100.00
V2	alert_test	kmac_alert_test	1.600s	17.242us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.100s	497.637us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.100s	497.637us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.780s	93.691us	1	1	100.00
		kmac_csr_rw	1.910s	59.056us	1	1	100.00
		kmac_csr_aliasing	5.950s	149.062us	1	1	100.00
		kmac_same_csr_outstanding	2.830s	224.104us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.780s	93.691us	1	1	100.00
		kmac_csr_rw	1.910s	59.056us	1	1	100.00
		kmac_csr_aliasing	5.950s	149.062us	1	1	100.00
		kmac_same_csr_outstanding	2.830s	224.104us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.270s	240.567us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.270s	240.567us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.270s	240.567us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.270s	240.567us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.930s	32.383us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	23.800s	3.380ms	1	1	100.00
		kmac_tl_intg_err	3.850s	928.547us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.850s	928.547us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.760s	152.166us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	44.010s	4.244ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.741m	9.427ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.270s	240.567us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	23.800s	3.380ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	23.800s	3.380ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	23.800s	3.380ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	44.010s	4.244ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.760s	152.166us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	23.800s	3.380ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.406m	22.674ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	44.010s	4.244ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.006m	4.312ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.91212294697017731447166424475353456622535126173164787521313959080950077809244
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @  32382630 ps: (kmac_csr_assert_fpv.sv:525) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @  32382630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---