872a98e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 1.033m | 1.231ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 176.678us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 26.488us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 295.367us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 32.262us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.879us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 26.488us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 32.262us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 18.000s | 619.577us | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 1.083m | 2.695ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 38.000s | 8.020ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 8.000s | 32.708us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 10.048us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 10.048us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 176.678us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 26.488us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 32.262us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 19.504us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 176.678us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 26.488us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 32.262us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 19.504us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 8.000s | 12.672us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 7.807us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.59287811269673717506853381809705606621141440264019098999063046475102362771316
Line 99, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 7807091 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xfdb113b3 a_data = 0x18654351 a_mask = 0x0 a_size = 0x2 a_param = 0x0 a_source = 0x95 a_opcode = Invalid, value: 3 a_user = 0x26c11 d_data = 0x196b0767 d_size = 0x3 d_param = 0x0 d_source = 0x62 d_opcode = AccessAckData d_error = 0 d_user = 1110010010 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 7807091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_csr_mem_rw_with_rand_reset has 1 failures.
0.mbx_csr_mem_rw_with_rand_reset.18186153509892701711252756815714317436052311051149149914401864719266489207628
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1878509 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x4cf37e30 a_data = 0x42fb4f7c a_mask = 0x0 a_size = 0x2 a_param = 0x0 a_source = 0x79 a_opcode = Invalid, value: 2 a_user = 0x27835 d_data = 0xf2c5376f d_size = 0x1 d_param = 0x0 d_source = 0xce d_opcode = AccessAckData d_error = 0 d_user = 100001101110 d_sink = 1 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1878509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.21781283903959601749667678728605566115115067982046596710750771484518935067427
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 10048060 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x24ad2bcc a_data = 0xdc42c7d0 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x78 a_opcode = PutFullData a_user = 0x1a5b9 d_data = 0x1730e26c d_size = 0x3 d_param = 0x0 d_source = 0x31 d_opcode = AccessAck d_error = 0 d_user = 11000110111 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 10048060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---