OTBN Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	84.108us	1	1	100.00
V1	single_binary	otbn_single	8.000s	18.640us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	75.174us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	16.203us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	76.249us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	48.859us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	42.560us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	16.203us	1	1	100.00
		otbn_csr_aliasing	6.000s	48.859us	1	1	100.00
V1	mem_walk	otbn_mem_walk	14.000s	661.485us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	1.008ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	17.000s	99.664us	1	1	100.00
V2	multi_error	otbn_multi_err	1.100m	248.191us	1	1	100.00
V2	back_to_back	otbn_multi	26.000s	230.397us	1	1	100.00
V2	stress_all	otbn_stress_all	1.133m	816.672us	1	1	100.00
V2	lc_escalation	otbn_escalate	11.000s	29.216us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	19.751us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	9.000s	29.383us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	91.117us	1	1	100.00
V2	intr_test	otbn_intr_test	8.000s	23.085us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	6.000s	54.881us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	6.000s	54.881us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	75.174us	1	1	100.00
		otbn_csr_rw	6.000s	16.203us	1	1	100.00
		otbn_csr_aliasing	6.000s	48.859us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	46.920us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	75.174us	1	1	100.00
		otbn_csr_rw	6.000s	16.203us	1	1	100.00
		otbn_csr_aliasing	6.000s	48.859us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	46.920us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	12.993us	1	1	100.00
		otbn_dmem_err	9.000s	66.760us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	110.728us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	54.845us	1	1	100.00
		otbn_mac_bignum_acc_err	2.233m	840.968us	1	1	100.00
		otbn_urnd_err	11.000s	22.608us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	27.738us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	54.633us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	6.000s	27.939us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
		otbn_tl_intg_err	12.000s	241.172us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	18.000s	73.782us	0	1	0.00
V2S	prim_fsm_check	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	84.108us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	66.760us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	12.993us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	12.000s	241.172us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	11.000s	29.216us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	12.993us	1	1	100.00
		otbn_dmem_err	9.000s	66.760us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	19.751us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	27.738us	1	1	100.00
		otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	18.640us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	12.993us	1	1	100.00
		otbn_dmem_err	9.000s	66.760us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	19.751us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	27.738us	1	1	100.00
		otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	11.000s	29.216us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	12.993us	1	1	100.00
		otbn_dmem_err	9.000s	66.760us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	19.751us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	27.738us	1	1	100.00
		otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	18.640us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	344.659us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	23.414us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.800m	377.474us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.800m	377.474us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	62.670us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	103.525us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	28.018us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	28.018us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	16.172us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	18.640us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	18.640us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	18.640us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	26.000s	230.397us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	18.640us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	18.640us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	94.478us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	18.640us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	2.967m	7.253ms	1	1	100.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	30.000s	285.981us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.96296262098263436400489283812301156498743037016076820942289957533459284109919
      Line 160, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 285981464 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 285981464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.27057059165635216570719110675713277856306707816679295239427331232059809006389
      Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16172490 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  16172490 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  16172490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test otbn_passthru_mem_tl_intg_err has 1 failures.

    • 0.otbn_passthru_mem_tl_intg_err.36839564385308508337929311511813002438702284768165691661561264134862980488492
      Line 102, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @  73782343 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  73782343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---