ROM_CTRL/32KB Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.250s 527.833us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.700s 543.838us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.050s 171.159us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.090s 165.602us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.970s 212.136us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 3.980s 766.013us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.050s 171.159us 1 1 100.00
rom_ctrl_csr_aliasing 4.970s 212.136us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.920s 167.080us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.820s 401.601us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.480s 183.574us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.010s 461.678us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.250s 221.918us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.210s 2.101ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.100s 159.734us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.100s 159.734us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.700s 543.838us 1 1 100.00
rom_ctrl_csr_rw 7.050s 171.159us 1 1 100.00
rom_ctrl_csr_aliasing 4.970s 212.136us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.450s 558.986us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.700s 543.838us 1 1 100.00
rom_ctrl_csr_rw 7.050s 171.159us 1 1 100.00
rom_ctrl_csr_aliasing 4.970s 212.136us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.450s 558.986us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 12.190s 1.525ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.894m 7.089ms 1 1 100.00
rom_ctrl_tl_intg_err 41.430s 546.685us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.894m 7.089ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.894m 7.089ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.894m 7.089ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.894m 7.089ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.250s 527.833us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.250s 527.833us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.250s 527.833us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 41.430s 546.685us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.250s 221.918us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 40.600s 1.304ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 12.190s 1.525ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.894m 7.089ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.050m 4.951ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00