RV_TIMER Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.480s	50.114us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.530s	18.598us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.420s	30.745us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.060s	92.755us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.640s	38.699us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.830s	22.268us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.420s	30.745us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	38.699us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	3.130s	1.076ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.870s	1.228ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.417m	149.043ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.417m	149.043ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.440s	985.363us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.410s	14.647us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.400s	65.136us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.030s	256.976us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.030s	256.976us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.530s	18.598us	1	1	100.00
		rv_timer_csr_rw	1.420s	30.745us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	38.699us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	21.594us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.530s	18.598us	1	1	100.00
		rv_timer_csr_rw	1.420s	30.745us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	38.699us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	21.594us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.910s	472.980us	1	1	100.00
		rv_timer_tl_intg_err	2.170s	83.253us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.170s	83.253us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	32.430s	16.557ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.410s	13.346us	1	1	100.00
		rv_timer_max	1.440s	13.676us	1	1	100.00
		TOTAL			19	19	100.00