SPI_DEVICE/1R1W Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	51.520s	6.143ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.770s	40.503us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.900s	113.421us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.430s	7.563ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.710s	2.644ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.210s	186.142us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.900s	113.421us	1	1	100.00
		spi_device_csr_aliasing	11.710s	2.644ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.600s	53.185us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.810s	27.139us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.750s	19.602us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.850s	2.075us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.560s	4.717us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.040s	19.527us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.040s	19.527us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	12.880s	19.161ms	1	1	100.00
		spi_device_tpm_sts_read	1.460s	32.007us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.640s	946.023us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.520s	286.956us	1	1	100.00
		spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.720s	767.964us	1	1	100.00
		spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.720s	767.964us	1	1	100.00
		spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.780s	449.213us	1	1	100.00
		spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.780s	449.213us	1	1	100.00
		spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.780s	449.213us	1	1	100.00
		spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.780s	449.213us	1	1	100.00
		spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.780s	449.213us	1	1	100.00
		spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.100s	1.972ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	10.300s	1.270ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	10.300s	1.270ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	10.300s	1.270ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.910s	1.384ms	1	1	100.00
		spi_device_read_buffer_direct	7.380s	5.150ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	10.300s	1.270ms	1	1	100.00
		spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.560s	16.477us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.590s	57.599us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.590s	57.599us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	51.520s	6.143ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	16.420s	2.530ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.231m	16.794ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.430s	18.565us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.520s	25.753us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.930s	54.979us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.930s	54.979us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.770s	40.503us	1	1	100.00
		spi_device_csr_rw	2.900s	113.421us	1	1	100.00
		spi_device_csr_aliasing	11.710s	2.644ms	1	1	100.00
		spi_device_same_csr_outstanding	2.310s	93.122us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.770s	40.503us	1	1	100.00
		spi_device_csr_rw	2.900s	113.421us	1	1	100.00
		spi_device_csr_aliasing	11.710s	2.644ms	1	1	100.00
		spi_device_same_csr_outstanding	2.310s	93.122us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.070s	357.195us	1	1	100.00
		spi_device_tl_intg_err	5.500s	411.042us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.500s	411.042us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.758m	149.477ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.112798009157967728410609879129227509098777633432127938102541686329637001293726
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1483277 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[16])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1483277 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1483277 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[912])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.96076873306989071597532729691199774916696234094522393414264003682261151949116
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2198426 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc5abdc [110001011010101111011100] vs 0x0 [0])
        UVM_ERROR @   2289426 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfab336 [111110101011001100110110] vs 0x0 [0])
        UVM_ERROR @   2292426 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe0d9df [111000001101100111011111] vs 0x0 [0])
        UVM_ERROR @   2348426 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc99b09 [110010011001101100001001] vs 0x0 [0])
        UVM_ERROR @   2392426 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x217d3d [1000010111110100111101] vs 0x0 [0])