SPI_HOST Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	15.000s	616.794us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	32.797us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	20.979us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	560.925us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	28.766us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	350.749us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	20.979us	1	1	100.00
		spi_host_csr_aliasing	4.000s	28.766us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	35.480us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	23.005us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	29.528us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	61.161us	1	1	100.00
		spi_host_error_cmd	3.000s	21.772us	1	1	100.00
		spi_host_event	23.000s	2.002ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	629.804us	1	1	100.00
V2	speed	spi_host_speed	5.000s	629.804us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	629.804us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	85.038us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	187.640us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	629.804us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	629.804us	1	1	100.00
V2	duplex	spi_host_smoke	15.000s	616.794us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	15.000s	616.794us	1	1	100.00
V2	stress_all	spi_host_stress_all	20.000s	1.119ms	1	1	100.00
V2	spien	spi_host_spien	14.000s	1.724ms	1	1	100.00
V2	stall	spi_host_status_stall	39.000s	1.168ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	644.292us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	61.161us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	15.249us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	36.515us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	194.361us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	194.361us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	32.797us	1	1	100.00
		spi_host_csr_rw	3.000s	20.979us	1	1	100.00
		spi_host_csr_aliasing	4.000s	28.766us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	22.210us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	32.797us	1	1	100.00
		spi_host_csr_rw	3.000s	20.979us	1	1	100.00
		spi_host_csr_aliasing	4.000s	28.766us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	22.210us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	209.664us	1	1	100.00
		spi_host_sec_cm	4.000s	156.275us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	209.664us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.250m	5.444ms	1	1	100.00
		TOTAL			26	26	100.00