SRAM_CTRL/MAIN Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 7.580s 1.457ms 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.660s 21.650us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.700s 31.370us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.970s 111.873us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.550s 19.470us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.610s 357.710us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.700s 31.370us 1 1 100.00
sram_ctrl_csr_aliasing 1.550s 19.470us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 1.914m 11.534ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 1.755m 4.470ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 10.678m 279.448ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 2.315m 7.587ms 1 1 100.00
V2 bijection sram_ctrl_bijection 9.804m 12.689ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 4.250m 27.323ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.178m 41.127ms 1 1 100.00
V2 executable sram_ctrl_executable 4.194m 13.556ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 10.810s 3.342ms 1 1 100.00
sram_ctrl_partial_access_b2b 3.168m 9.598ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 12.060s 720.842us 1 1 100.00
sram_ctrl_throughput_w_partial_write 10.400s 746.227us 1 1 100.00
sram_ctrl_throughput_w_readback 56.090s 954.266us 1 1 100.00
V2 regwen sram_ctrl_regwen 3.761m 8.747ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 3.220s 346.916us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 17.538m 95.093ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.490s 28.969us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.010s 174.029us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.010s 174.029us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.660s 21.650us 1 1 100.00
sram_ctrl_csr_rw 1.700s 31.370us 1 1 100.00
sram_ctrl_csr_aliasing 1.550s 19.470us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.590s 41.929us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.660s 21.650us 1 1 100.00
sram_ctrl_csr_rw 1.700s 31.370us 1 1 100.00
sram_ctrl_csr_aliasing 1.550s 19.470us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.590s 41.929us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 30.920s 29.544ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.810s 750.883ns 0 1 0.00
sram_ctrl_tl_intg_err 3.010s 216.611us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.810s 750.883ns 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.010s 216.611us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 3.761m 8.747ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 3.761m 8.747ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.700s 31.370us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 4.194m 13.556ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 4.194m 13.556ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 4.194m 13.556ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.178m 41.127ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 5.270s 714.930us 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 30.920s 29.544ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 5.360s 1.788ms 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 7.580s 1.457ms 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 7.580s 1.457ms 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 4.194m 13.556ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.810s 750.883ns 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.178m 41.127ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.810s 750.883ns 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.810s 750.883ns 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 7.580s 1.457ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.810s 750.883ns 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 10.520s 417.937us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets