SRAM_CTRL/RET Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.350s	320.614us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.590s	33.811us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.430s	13.380us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.200s	47.182us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.560s	21.408us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.900s	94.451us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.430s	13.380us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	21.408us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.920s	3.439ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.020s	326.862us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	10.628m	56.049ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.540m	1.341ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	47.980s	3.337ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.287m	1.259ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.970s	1.316ms	1	1	100.00
V2	executable	sram_ctrl_executable	12.343m	15.456ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.600s	751.344us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.230m	68.366ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	22.110s	427.517us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	31.040s	242.559us	1	1	100.00
		sram_ctrl_throughput_w_readback	8.670s	105.706us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.465m	10.820ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.580s	27.862us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	23.030s	1.450ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.500s	151.334us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.500s	41.620us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.500s	41.620us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.590s	33.811us	1	1	100.00
		sram_ctrl_csr_rw	1.430s	13.380us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	21.408us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	23.488us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.590s	33.811us	1	1	100.00
		sram_ctrl_csr_rw	1.430s	13.380us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	21.408us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	23.488us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.210s	799.448us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.400s	4.243us	0	1	0.00
		sram_ctrl_tl_intg_err	1.970s	367.479us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.400s	4.243us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.970s	367.479us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.465m	10.820ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.465m	10.820ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.430s	13.380us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.343m	15.456ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.343m	15.456ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.343m	15.456ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.970s	1.316ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.780s	156.982us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.210s	799.448us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.120s	24.122us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.350s	320.614us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.350s	320.614us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.343m	15.456ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.400s	4.243us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.970s	1.316ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.400s	4.243us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.400s	4.243us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.350s	320.614us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.400s	4.243us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	58.880s	728.290us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.41846235389805425296097456885753998503680588709591437375095138835841234071464
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  24122428 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x49) != exp (0x60)
        UVM_INFO @  24122428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.51703200810128770504920234671842893067010337468295803426800334881345420632609
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4243122 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4243122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.15232892094044487452057058364364881292159134707281897471140753154283006306827
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  94450823 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0
        UVM_INFO @  94450823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---