UART Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.490s	861.126us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.490s	85.887us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.450s	19.233us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.980s	121.763us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.690s	49.546us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.560s	57.254us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.450s	19.233us	1	1	100.00
		uart_csr_aliasing	1.690s	49.546us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	57.070s	50.242ms	1	1	100.00
V2	parity	uart_smoke	2.490s	861.126us	1	1	100.00
		uart_tx_rx	57.070s	50.242ms	1	1	100.00
V2	parity_error	uart_intr	10.330s	23.699ms	1	1	100.00
		uart_rx_parity_err	1.839m	172.802ms	1	1	100.00
V2	watermark	uart_tx_rx	57.070s	50.242ms	1	1	100.00
		uart_intr	10.330s	23.699ms	1	1	100.00
V2	fifo_full	uart_fifo_full	10.190s	60.642ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	26.580s	23.278ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	15.210s	57.565ms	1	1	100.00
V2	rx_frame_err	uart_intr	10.330s	23.699ms	1	1	100.00
V2	rx_break_err	uart_intr	10.330s	23.699ms	1	1	100.00
V2	rx_timeout	uart_intr	10.330s	23.699ms	1	1	100.00
V2	perf	uart_perf	1.619m	14.392ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.250s	15.353ms	1	1	100.00
V2	line_loopback	uart_loopback	4.250s	15.353ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	27.680s	126.915ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.050s	606.713us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	10.600s	7.850ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	9.120s	2.106ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.296m	33.847ms	1	1	100.00
V2	stress_all	uart_stress_all	29.750s	56.234ms	1	1	100.00
V2	alert_test	uart_alert_test	1.410s	21.087us	1	1	100.00
V2	intr_test	uart_intr_test	1.450s	26.694us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.490s	92.370us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.490s	92.370us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.490s	85.887us	1	1	100.00
		uart_csr_rw	1.450s	19.233us	1	1	100.00
		uart_csr_aliasing	1.690s	49.546us	1	1	100.00
		uart_same_csr_outstanding	1.550s	16.465us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.490s	85.887us	1	1	100.00
		uart_csr_rw	1.450s	19.233us	1	1	100.00
		uart_csr_aliasing	1.690s	49.546us	1	1	100.00
		uart_same_csr_outstanding	1.550s	16.465us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	2.060s	1.098ms	1	1	100.00
		uart_tl_intg_err	1.910s	346.173us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.910s	346.173us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	12.210s	4.154ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00