CHIP Simulation Results

Tuesday May 27 2025 17:01:21 UTC

GitHub Revision: `872a98e`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.220m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.220m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.205m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.673m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.019m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.067m	5.697ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.067m	5.697ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.067m	5.697ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	45.040s	10.180us	0	1	0.00
		chip_sw_example_manufacturer	2.593m		0	1	0.00
		chip_sw_example_concurrency	4.042m	3.408ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.393s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.120s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.620s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.620s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.210s	55.002us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.561m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.824m	7.309ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.761m	4.078ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.202s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.896s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	55.499s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.092m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.520s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.520s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.196m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.148m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.708m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.708m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.615m	4.933ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.076m	3.789ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.224m	14.440ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.638s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.704s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	18.247m	21.534ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.588m	5.090ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.630m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.630m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.280s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.655m	4.819ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.655m	4.819ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.444m	18.018ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.817m	5.985ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.338m	4.535ms	1	1	100.00
		chip_sw_aes_idle	4.952m	5.330ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.956m	4.763ms	1	1	100.00
		chip_sw_kmac_idle	3.756m	5.833ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.430m	12.020ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.302m	12.023ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.398m	12.024ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.448m	12.018ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.589s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.225s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.590s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.357s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.628s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.730s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.560s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.589s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.225s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.590s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.357s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.628s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.730s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.560s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.376s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.034m	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.590s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.000m	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	47.040s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.042s		0	1	0.00
		chip_sw_clkmgr_jitter	3.333m	4.025ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.500m	5.621ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.327s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	53.360s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.810s	10.280us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	48.370s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	50.890s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	46.150s	10.240us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.659s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.924s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	15.907s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.202s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.370m	16.558ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.543m	11.815ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.655m	4.819ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	15.102s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.543m	11.815ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.917s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	15.228s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	13.286s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.809s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.491s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.370m	16.558ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.224m	14.440ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	22.318m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.738m	8.555ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.551m	6.978ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.466m	5.358ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.370m	16.558ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.644s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.931s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.370m	16.558ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.415s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.551m	6.978ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.830s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.007s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.904s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.368s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.818s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.682s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.931s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	20.928s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	22.394s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	20.928s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	20.928s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	20.928s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.377m	8.141ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.333s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.937s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.310s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	36.027s		0	1	0.00
		chip_sw_lc_ctrl_transition	20.928s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.646m	8.656ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.370m	11.767ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.465s		0	1	0.00
		chip_prim_tl_access	8.916m	12.139ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.589s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.225s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.590s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.357s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.628s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.730s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.560s		0	1	0.00
		chip_rv_dm_lc_disabled	18.247m	21.534ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.667m	3.311ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.034m	10.400us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.473m	3.390ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.952m	5.330ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.928m	5.634ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	46.590s	10.360us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.956m	4.763ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.937m	5.824ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.804m	6.113ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	47.040s	10.380us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.646m	8.656ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	20.928s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	47.880s	10.100us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.338m	5.829ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.756m	5.833ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.072s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.072s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.429s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.068m	4.098ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.533s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.646m	8.656ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.000m	10.180us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.168s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.376s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.338m	4.535ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.338m	4.535ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.338m	4.535ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.283m	6.415ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.370m	11.767ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.370m	11.767ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.531m	5.691ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.042s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.465s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.370m	16.558ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.708m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	20.928s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.283m	6.415ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.646m	8.656ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.531m	5.691ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.091m	3.331ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.283m	6.415ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.646m	8.656ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.531m	5.691ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.091m	3.331ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	20.928s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.473s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	22.394s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.333s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.937s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.310s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	36.027s		0	1	0.00
		chip_sw_lc_ctrl_transition	20.928s		0	1	0.00
		chip_prim_tl_access	8.916m	12.139ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.916m	12.139ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	15.711s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	15.416s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.924s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.376s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.034m	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.590s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.000m	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	47.040s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.042s		0	1	0.00
		chip_sw_clkmgr_jitter	3.333m	4.025ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.529m	6.601ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.529m	6.601ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.524m	4.283ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.429m	4.350ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.494m	5.345ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.962m	6.991ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.965m	4.172ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.152m	4.290ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.091m	3.331ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	22.318m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	22.318m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.228m	5.965ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.888m	5.776ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.595m	4.557ms	1	1	100.00
		chip_sw_csrng_smoketest	3.221m	5.154ms	1	1	100.00
		chip_sw_gpio_smoketest	4.030m	4.778ms	1	1	100.00
		chip_sw_hmac_smoketest	4.819m	5.281ms	1	1	100.00
		chip_sw_kmac_smoketest	3.760m	5.116ms	1	1	100.00
		chip_sw_otbn_smoketest	3.968m	5.698ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.604m	3.990ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.551m	3.767ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.745m	4.861ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.512m	4.189ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.445m	3.893ms	1	1	100.00
		chip_sw_uart_smoketest	3.983m	5.518ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.686s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.393s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.561m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.233s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.940m	5.186ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.909m	5.757ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.167m	5.241ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.143m	5.913ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	15.207s		0	1	0.00
		chip_rv_dm_lc_disabled	18.247m	21.534ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.309s		0	1	0.00
		chip_sw_lc_walkthrough_prod	16.330s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	19.086s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.331s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	15.207s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.603s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	16.593s		0	1	0.00
		rom_volatile_raw_unlock	10.320s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.624s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.348m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.511m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.773m	3.775ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.773m	3.775ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.620s		0	1	0.00
		chip_same_csr_outstanding	9.570s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.620s		0	1	0.00
		chip_same_csr_outstanding	9.570s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	51.160s	43.905us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.950s	12.416us	1	1	100.00
		xbar_smoke_large_delays	4.151m	2.201ms	1	1	100.00
		xbar_smoke_slow_rsp	5.301m	2.022ms	1	1	100.00
		xbar_random_zero_delays	27.750s	25.179us	1	1	100.00
		xbar_random_large_delays	22.284m	11.621ms	1	1	100.00
		xbar_random_slow_rsp	31.815m	12.466ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	10.010s	16.764us	1	1	100.00
		xbar_error_and_unmapped_addr	20.580s	44.028us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.162m	70.223us	1	1	100.00
		xbar_error_and_unmapped_addr	20.580s	44.028us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.591m	797.910us	1	1	100.00
		xbar_access_same_device_slow_rsp	18.532m	6.603ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	32.440s	60.872us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	13.156m	1.919ms	1	1	100.00
		xbar_stress_all_with_error	9.636m	1.771ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	52.150s	65.591us	1	1	100.00
		xbar_stress_all_with_reset_error	8.590m	499.750us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.831s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.814s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.908s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.298s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.383s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.731s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.912s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.684s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.608s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.113s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.144s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.085s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.524s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.797s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.248s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.442s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.767s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.146s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.080s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.118s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.405s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.450s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.938s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.160s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.576s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.030s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	14.139s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.870s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.969s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.972s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.385s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.916s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.804s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.747s		0	1	0.00
		rom_e2e_asm_init_dev	11.525s		0	1	0.00
		rom_e2e_asm_init_prod	12.558s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.031s		0	1	0.00
		rom_e2e_asm_init_rma	11.429s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.374s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.552s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.781s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.416s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.158m	4.853ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.246m	5.306ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.442s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.059s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.954s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.154s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.370m	16.558ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	38.995s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.786m	17.363ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.556s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.711s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.442s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.059s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.954s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.029s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.544s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.416s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.317m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.947m	15.335ms	1	1	100.00
		chip_plic_all_irqs_0	10.367m	7.206ms	1	1	100.00
		chip_plic_all_irqs_10	10.510m	6.480ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.314m	5.818ms	1	1	100.00
		chip_sw_dma_abort	4.683m	4.530ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.322s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.479s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.295s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.392s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.516s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.409s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.407s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.581s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.427s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.399s		0	1	0.00
		chip_sw_mbx_smoketest	4.389m	5.549ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.19193430213581663505338309954087110679917498026265565438146476160931806362592
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (40338c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 136.141s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.54397812488280970851128901379822604764363325406888303666320855222587539077253
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b50648)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 152.220s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.38524442974168871238565111946496895087060332502763279218439141323546993310538
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (f5c3fb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 120.895s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.27641729722204249282771184258706393724584395135880906282282324759234203365425
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b04c55)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 117.310s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.32194081673025385025614412194052073597734882258619187817705799531776753589672
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (d41928)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 122.714s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.16859027852439922459321381551914426548190268411578165115990702159643098483032
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.114211524009623402121369962950071269829401270105155883432261843044745830118681
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.76205973925409728560278741378868323265673729698408044924189246516980150917141
    Line 411, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.49378933702419349919810023760340611082748611773496583198142793540721894765429
    Line 413, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.4641234265978031202362875784918757013581219228551630119487772898421943009244
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.72358085837243626927299630584260842575110347170178655548388564924365338148038
Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12020.261533 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12020.261533 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.38358650390332642502119459370756648192099408558992221730217746597595870520734
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12022.677811 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.677811 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.26653764211243810368307969251618447768382361167623527581280386943530375518554
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12023.501191 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12023.501191 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.68732351495559392834103109047970339026523744590311594423710339741848655212569
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12017.614606 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.614606 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.115149373871840628956426373716238595074606085454798381840203302447294184574225
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.28597153612340838142908306136806542690827901757607625936542570001947093872905
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.57315134452797732567825296550230186296261476846811322045992895328151546382203
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.27805805777559305699038280293339646579875672372789882766603295017440333330869
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20017.849752 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20017.849752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.10632178432449608771944136375287307725376958390852740579656008984369327881362
Line 438, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.829690 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.829690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.72691872378427479629273506636408881774750283541817576038113535191418994948295
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18017.519010 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.519010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.112058255670153247069437405703566594621364806655099459377079935371104731211014
Line 475, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8656.110106 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (60913687896750854456837700179089982924469884863994011230396683852952118135892 [0x86abecf213aa9c502af2980fe66e95f85c48061f10d3595079d73e886f0a8c54] vs 36020128578509066198071696068192403420946235496068616381683998775874523912783 [0x4fa2ab98b83620c8f0d909fe1f3d785eb8af39f5dfaaa63c3c07c14caf265a4f])
  UVM_INFO @ 8656.110106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.37693185598435156615773083197999455686446814520180557100644115429497065029693
Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8141.477016 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (24358967991049256955896851461623679894838768476311299544255277376944158892854 [0x35daaff2f7cd7cdb8c7d22c128a934fe547be45eba9c9fa92f7430c125156336] vs 45200538737488951932359595789036896776380284702086686002236145112176478037106 [0x63ee992afeaa9af566f9510609511e3c258af2f2dcdbfd690050c45a5efea472])
  UVM_INFO @ 8141.477016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.105393839913730499327934239649298665331838271333694117415720552367011993531135
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4932.971214 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hc2fb0928  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h0  a_user: 'h2692f  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4932.971214 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.98539660537255911870301757707768524498822366938694836476501627137657212646167
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3788.732579 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hea3c2efb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3d  a_opcode: 'h0  a_user: 'h26920  d_param: 'h0  d_source: 'h3d  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3788.732579 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.10605992140803694972234723027595157984735071445535119536422195646298321374134
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.64527892023113313403915154353309682111601874046683574271772651960744888674640
    Line 469, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4077.539260 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4077.539260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.27512916815983516597296558750162288911959892031816110001534625797480833190217
    Line 659, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6978.286006 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6978.286006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.87101406101826652073516846189247320144356653477252988004268609396031806131505
    Line 438, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4283.238630 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4283.238630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.112206702622135935111867525846827949822391505111514336144921583928611769075683
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4349.717800 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4349.717800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.95801229564953452933987923756508508085115266946774057438993014621180399157305
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4818.574624 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4818.574624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.9669461016307144469814572309800954048983722687349580648918364253256616237166
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6991.035164 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6991.035164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.90446237575819613376344037241664607580189789434056659206397454455870452149915
    Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36576) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.104057903455549752488886347416188646141817600860991722928374800055866762735592
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3775.053166 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36576) { a_addr: 'h2212  a_data: 'h3b4df3ac  a_mask: 'h8  a_size: 'h1  a_param: 'h0  a_source: 'hac  a_opcode: 'h4  a_user: 'h25005  d_param: 'h0  d_source: 'hac  d_data: 'h0  d_size: 'h1  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h12a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3775.053166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.22385073449753839029101413423717828315894092075368783431728170999310322322759
    Line 405, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14440.367680 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14440.367680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.109347341872489502217176445039864344481798426895177001042201561861444480287720
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.114046497995794565226362515397585124214253605742777591785874974356782663147658
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4529.982012 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4529.982012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```