DMA Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	334.995us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	286.505us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	853.953us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	211.305us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	32.354us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	502.627us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	11.000s	2.355ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	29.729us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	32.354us	1	1	100.00
		dma_csr_aliasing	11.000s	2.355ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	52.000s	6.105ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	4.767m	56.124ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	1.883m	37.371ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	58.583m	828.356ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	4.767m	56.124ms	1	1	100.00
V2	dma_abort	dma_abort	15.000s	921.710us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.617m	7.403ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	13.684us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	323.019us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	323.019us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	211.305us	1	1	100.00
		dma_csr_rw	4.000s	32.354us	1	1	100.00
		dma_csr_aliasing	11.000s	2.355ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	242.566us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	211.305us	1	1	100.00
		dma_csr_rw	4.000s	32.354us	1	1	100.00
		dma_csr_aliasing	11.000s	2.355ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	242.566us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	17.000s	178.215us	1	1	100.00
		dma_generic_stress	58.583m	828.356ms	1	1	100.00
		dma_handshake_stress	4.767m	56.124ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	239.547us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.033m	10.642ms	1	1	100.00
		dma_longer_transfer	14.000s	7.338ms	1	1	100.00
		TOTAL			21	21	100.00