EDN Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.070s	31.818us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	2.230s	19.763us	1	1	100.00
V1	csr_rw	edn_csr_rw	2.120s	41.691us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.000s	385.203us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.990s	20.349us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.080s	114.015us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	2.120s	41.691us	1	1	100.00
		edn_csr_aliasing	1.990s	20.349us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.610s	33.221us	1	1	100.00
V2	csrng_commands	edn_genbits	2.610s	33.221us	1	1	100.00
V2	genbits	edn_genbits	2.610s	33.221us	1	1	100.00
V2	interrupts	edn_intr	1.820s	25.897us	1	1	100.00
V2	alerts	edn_alert	2.460s	28.164us	1	1	100.00
V2	errs	edn_err	1.970s	22.507us	1	1	100.00
V2	disable	edn_disable	1.750s	24.399us	1	1	100.00
		edn_disable_auto_req_mode	2.520s	45.951us	1	1	100.00
V2	stress_all	edn_stress_all	3.630s	979.588us	1	1	100.00
V2	intr_test	edn_intr_test	1.900s	23.627us	1	1	100.00
V2	alert_test	edn_alert_test	1.750s	47.038us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.490s	77.158us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.490s	77.158us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	2.230s	19.763us	1	1	100.00
		edn_csr_rw	2.120s	41.691us	1	1	100.00
		edn_csr_aliasing	1.990s	20.349us	1	1	100.00
		edn_same_csr_outstanding	2.120s	22.012us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	2.230s	19.763us	1	1	100.00
		edn_csr_rw	2.120s	41.691us	1	1	100.00
		edn_csr_aliasing	1.990s	20.349us	1	1	100.00
		edn_same_csr_outstanding	2.120s	22.012us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	7.520s	1.257ms	1	1	100.00
		edn_tl_intg_err	2.860s	561.352us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	2.120s	45.381us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.460s	28.164us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.520s	1.257ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.520s	1.257ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.520s	1.257ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.520s	1.257ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.460s	28.164us	1	1	100.00
		edn_sec_cm	7.520s	1.257ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.460s	28.164us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.860s	561.352us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.364m	4.401ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00