HMAC Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.700s 184.942us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.580s 38.860us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.480s 24.843us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.030s 5.670ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.940s 228.077us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.080s 32.281us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.480s 24.843us 1 1 100.00
hmac_csr_aliasing 2.940s 228.077us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 15.910s 1.456ms 1 1 100.00
V2 back_pressure hmac_back_pressure 4.160s 338.360us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.570s 177.453us 1 1 100.00
hmac_test_sha384_vectors 7.055m 48.768ms 1 1 100.00
hmac_test_sha512_vectors 6.908m 94.117ms 1 1 100.00
hmac_test_hmac256_vectors 8.480s 507.519us 1 1 100.00
hmac_test_hmac384_vectors 7.150s 1.003ms 1 1 100.00
hmac_test_hmac512_vectors 6.760s 166.879us 1 1 100.00
V2 burst_wr hmac_burst_wr 3.900s 81.458us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 14.889m 5.784ms 1 1 100.00
V2 error hmac_error 4.050s 662.251us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 43.060s 8.602ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.700s 184.942us 1 1 100.00
hmac_long_msg 15.910s 1.456ms 1 1 100.00
hmac_back_pressure 4.160s 338.360us 1 1 100.00
hmac_datapath_stress 14.889m 5.784ms 1 1 100.00
hmac_burst_wr 3.900s 81.458us 1 1 100.00
hmac_stress_all 1.223m 30.950ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.700s 184.942us 1 1 100.00
hmac_long_msg 15.910s 1.456ms 1 1 100.00
hmac_back_pressure 4.160s 338.360us 1 1 100.00
hmac_datapath_stress 14.889m 5.784ms 1 1 100.00
hmac_wipe_secret 43.060s 8.602ms 1 1 100.00
hmac_test_sha256_vectors 8.570s 177.453us 1 1 100.00
hmac_test_sha384_vectors 7.055m 48.768ms 1 1 100.00
hmac_test_sha512_vectors 6.908m 94.117ms 1 1 100.00
hmac_test_hmac256_vectors 8.480s 507.519us 1 1 100.00
hmac_test_hmac384_vectors 7.150s 1.003ms 1 1 100.00
hmac_test_hmac512_vectors 6.760s 166.879us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.700s 184.942us 1 1 100.00
hmac_long_msg 15.910s 1.456ms 1 1 100.00
hmac_back_pressure 4.160s 338.360us 1 1 100.00
hmac_datapath_stress 14.889m 5.784ms 1 1 100.00
hmac_burst_wr 3.900s 81.458us 1 1 100.00
hmac_error 4.050s 662.251us 1 1 100.00
hmac_wipe_secret 43.060s 8.602ms 1 1 100.00
hmac_test_sha256_vectors 8.570s 177.453us 1 1 100.00
hmac_test_sha384_vectors 7.055m 48.768ms 1 1 100.00
hmac_test_sha512_vectors 6.908m 94.117ms 1 1 100.00
hmac_test_hmac256_vectors 8.480s 507.519us 1 1 100.00
hmac_test_hmac384_vectors 7.150s 1.003ms 1 1 100.00
hmac_test_hmac512_vectors 6.760s 166.879us 1 1 100.00
hmac_stress_all 1.223m 30.950ms 1 1 100.00
V2 stress_all hmac_stress_all 1.223m 30.950ms 1 1 100.00
V2 alert_test hmac_alert_test 1.510s 15.474us 1 1 100.00
V2 intr_test hmac_intr_test 1.380s 13.891us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.690s 457.050us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.690s 457.050us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.580s 38.860us 1 1 100.00
hmac_csr_rw 1.480s 24.843us 1 1 100.00
hmac_csr_aliasing 2.940s 228.077us 1 1 100.00
hmac_same_csr_outstanding 2.570s 376.192us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.580s 38.860us 1 1 100.00
hmac_csr_rw 1.480s 24.843us 1 1 100.00
hmac_csr_aliasing 2.940s 228.077us 1 1 100.00
hmac_same_csr_outstanding 2.570s 376.192us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.760s 124.493us 1 1 100.00
hmac_tl_intg_err 3.060s 154.411us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.060s 154.411us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.700s 184.942us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.010s 442.621us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.609m 12.283ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.810s 123.048us 1 1 100.00
TOTAL 28 28 100.00