I2C Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	24.330s	2.424ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.560s	438.507us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.520s	99.959us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.580s	27.184us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.470s	908.321us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.210s	43.443us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.900s	26.585us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.580s	27.184us	1	1	100.00
		i2c_csr_aliasing	2.210s	43.443us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.210s	139.008us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	25.232m	103.891ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	14.410s	4.093ms	1	1	100.00
V2	host_override	i2c_host_override	1.840s	51.482us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.396m	10.214ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	31.360s	15.547ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.940s	489.448us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.750s	332.827us	1	1	100.00
		i2c_host_fifo_reset_rx	6.220s	2.380ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	35.310s	8.209ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	14.100s	877.605us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.900s	514.680us	1	1	100.00
V2	target_glitch	i2c_target_glitch	6.710s	2.873ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	44.360s	32.889ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.480s	618.882us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	6.220s	580.817us	1	1	100.00
		i2c_target_intr_smoke	5.420s	1.003ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.760s	433.617us	1	1	100.00
		i2c_target_fifo_reset_tx	1.830s	649.897us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	5.920s	12.961ms	1	1	100.00
		i2c_target_stress_rd	6.220s	580.817us	1	1	100.00
		i2c_target_intr_stress_wr	1.253m	14.759ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.500s	3.854ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	13.320s	4.836ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.590s	4.948ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	5.980s	10.483ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.850s	626.632us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.220s	554.219us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	14.410s	4.093ms	1	1	100.00
		i2c_host_perf_precise	10.820s	709.202us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	14.100s	877.605us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.440s	226.323us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.070s	729.850us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.600s	1.887ms	1	1	100.00
		i2c_target_nack_txstretch	2.070s	335.053us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.590s	1.983ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.490s	1.438ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.390s	16.720us	1	1	100.00
V2	intr_test	i2c_intr_test	1.580s	53.045us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.600s	77.446us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.600s	77.446us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.520s	99.959us	1	1	100.00
		i2c_csr_rw	1.580s	27.184us	1	1	100.00
		i2c_csr_aliasing	2.210s	43.443us	1	1	100.00
		i2c_same_csr_outstanding	1.610s	31.601us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.520s	99.959us	1	1	100.00
		i2c_csr_rw	1.580s	27.184us	1	1	100.00
		i2c_csr_aliasing	2.210s	43.443us	1	1	100.00
		i2c_same_csr_outstanding	1.610s	31.601us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.150s	75.108us	1	1	100.00
		i2c_sec_cm	1.680s	47.528us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.150s	75.108us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	16.380s	2.059ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.320s	787.590us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.180s	2.094ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 2 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.12812595181629426854471435133598769472581468842339616897471216200330826131731
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 787590029 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 33 [0x21])
        UVM_INFO @ 787590029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.83295316736681777060392420091092636123412437771777678729076055280482863180111
      Line 101, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2093797880 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 18 [0x12])
        UVM_INFO @ 2093797880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.93449565083021935432498667105818427270369029847269672908874064054903943078714
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10482953478 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10482953478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.18308698373878270765547565310190659654712378030018666159409567066513477435319
      Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2059410493 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2059410493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---