KEYMGR Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	5.580s	946.598us	1	1	100.00
V1	random	keymgr_random	2.670s	122.514us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.760s	54.952us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.740s	43.790us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	4.820s	2.085ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	6.080s	489.179us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.640s	60.635us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.740s	43.790us	1	1	100.00
		keymgr_csr_aliasing	6.080s	489.179us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	2.860s	58.767us	1	1	100.00
V2	sideload	keymgr_sideload	1.560s	23.671us	0	1	0.00
		keymgr_sideload_kmac	5.700s	1.428ms	1	1	100.00
		keymgr_sideload_aes	2.620s	32.314us	1	1	100.00
		keymgr_sideload_otbn	2.840s	196.686us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.600s	119.289us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.360s	617.514us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.490s	223.357us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.550s	198.761us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.750s	110.875us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	8.230s	3.145ms	1	1	100.00
V2	stress_all	keymgr_stress_all	16.240s	1.632ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.600s	11.714us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.660s	13.510us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.970s	191.752us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.970s	191.752us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.760s	54.952us	1	1	100.00
		keymgr_csr_rw	1.740s	43.790us	1	1	100.00
		keymgr_csr_aliasing	6.080s	489.179us	1	1	100.00
		keymgr_same_csr_outstanding	2.720s	152.384us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.760s	54.952us	1	1	100.00
		keymgr_csr_rw	1.740s	43.790us	1	1	100.00
		keymgr_csr_aliasing	6.080s	489.179us	1	1	100.00
		keymgr_same_csr_outstanding	2.720s	152.384us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
		keymgr_tl_intg_err	5.010s	380.208us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.190s	896.590us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.190s	896.590us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.190s	896.590us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.190s	896.590us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.960s	117.460us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.010s	380.208us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.190s	896.590us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.860s	58.767us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.670s	122.514us	1	1	100.00
		keymgr_csr_rw	1.740s	43.790us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.670s	122.514us	1	1	100.00
		keymgr_csr_rw	1.740s	43.790us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.670s	122.514us	1	1	100.00
		keymgr_csr_rw	1.740s	43.790us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.360s	617.514us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.750s	110.875us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.750s	110.875us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.670s	122.514us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	4.030s	211.591us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	25.640s	5.151ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.360s	617.514us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	25.640s	5.151ms	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	25.640s	5.151ms	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	25.640s	5.151ms	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.280s	504.365us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	25.640s	5.151ms	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.980s	497.331us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.56022313470802944860252393488256531516294104702540305703658561476969897314564
      Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
        UVM_ERROR @ 117459693 ps: (keymgr_csr_assert_fpv.sv:419) [ASSERT FAILED] sealing_sw_binding_5_rd_A
        UVM_INFO @ 117459693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.77563431124017644725301417314245491090257040351176424893191801358068776996475
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
        UVM_ERROR @ 2084973849 ps: (keymgr_csr_assert_fpv.sv:394) [ASSERT FAILED] sealing_sw_binding_0_rd_A
        UVM_INFO @ 2084973849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.78457143846675028932604808820443437543613531049502006547401122894519493847838
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
        UVM_ERROR @  60635373 ps: (keymgr_csr_assert_fpv.sv:439) [ASSERT FAILED] attest_sw_binding_1_rd_A
        UVM_INFO @  60635373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_sideload has 1 failures.

    • 0.keymgr_sideload.12625912782018809909532513256445163315100038736362617388955282898826731040343
      Line 84, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_sideload/latest/run.log

        UVM_ERROR @  23671314 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @  23671314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---