KMAC/MASKED Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	35.260s	1.264ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.850s	34.995us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.860s	17.348us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.340s	1.451ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.740s	1.204ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.920s	363.534us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.860s	17.348us	1	1	100.00
		kmac_csr_aliasing	7.740s	1.204ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.740s	34.147us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.190s	40.748us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	13.251m	46.387ms	1	1	100.00
V2	burst_write	kmac_burst_write	15.490m	22.563ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.096m	240.296ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.949m	302.857ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.298m	185.710ms	1	1	100.00
		kmac_test_vectors_sha3_512	18.590s	2.615ms	1	1	100.00
		kmac_test_vectors_shake_128	34.302m	559.619ms	1	1	100.00
		kmac_test_vectors_shake_256	4.888m	11.272ms	1	1	100.00
		kmac_test_vectors_kmac	4.000s	89.303us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.920s	80.232us	1	1	100.00
V2	sideload	kmac_sideload	5.302m	73.419ms	1	1	100.00
V2	app	kmac_app	2.824m	14.181ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.209m	10.300ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.041m	49.967ms	1	1	100.00
V2	error	kmac_error	5.488m	18.406ms	1	1	100.00
V2	key_error	kmac_key_error	5.070s	1.249ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.900s	92.033us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	22.690s	7.641ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.790s	54.839us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	10.350s	975.668us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.970s	30.401us	1	1	100.00
V2	stress_all	kmac_stress_all	2.385m	24.137ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.830s	12.848us	1	1	100.00
V2	alert_test	kmac_alert_test	2.130s	25.015us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.500s	107.091us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.500s	107.091us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.850s	34.995us	1	1	100.00
		kmac_csr_rw	1.860s	17.348us	1	1	100.00
		kmac_csr_aliasing	7.740s	1.204ms	1	1	100.00
		kmac_same_csr_outstanding	2.340s	69.729us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.850s	34.995us	1	1	100.00
		kmac_csr_rw	1.860s	17.348us	1	1	100.00
		kmac_csr_aliasing	7.740s	1.204ms	1	1	100.00
		kmac_same_csr_outstanding	2.340s	69.729us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.140s	228.988us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.140s	228.988us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.140s	228.988us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.140s	228.988us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.990s	72.980us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	40.580s	14.800ms	1	1	100.00
		kmac_tl_intg_err	3.200s	384.674us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.200s	384.674us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.970s	30.401us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	35.260s	1.264ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.302m	73.419ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.140s	228.988us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	40.580s	14.800ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	40.580s	14.800ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	40.580s	14.800ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	35.260s	1.264ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.970s	30.401us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	40.580s	14.800ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	51.930s	3.208ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	35.260s	1.264ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	50.220s	9.083ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.90966244279528582969420798120632568528853237362479425883616150314538610242990
      Line 115, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9082789786 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9082789786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.94030770321422984344681473186961998769899460100367187572364181864695019076998
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @  72980255 ps: (kmac_csr_assert_fpv.sv:525) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @  72980255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---