KMAC/UNMASKED Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.880s	461.903us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.680s	51.916us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.820s	98.444us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.090s	294.822us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.880s	135.089us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.980s	317.703us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.820s	98.444us	1	1	100.00
		kmac_csr_aliasing	5.880s	135.089us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.520s	36.802us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.050s	131.845us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	13.942m	85.845ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.652m	8.109ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.240s	3.369ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.340s	6.030ms	1	1	100.00
		kmac_test_vectors_sha3_384	13.276m	52.076ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.680s	3.819ms	1	1	100.00
		kmac_test_vectors_shake_128	2.283m	54.124ms	1	1	100.00
		kmac_test_vectors_shake_256	1.102m	1.581ms	1	1	100.00
		kmac_test_vectors_kmac	2.700s	464.605us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.140s	97.593us	1	1	100.00
V2	sideload	kmac_sideload	3.779m	50.201ms	1	1	100.00
V2	app	kmac_app	52.160s	6.087ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.596m	8.252ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.740s	1.213ms	1	1	100.00
V2	error	kmac_error	12.510s	3.269ms	1	1	100.00
V2	key_error	kmac_key_error	2.260s	281.071us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.270s	159.356us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	11.870s	650.356us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	3.800s	381.807us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	30.440s	3.716ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.750s	46.638us	1	1	100.00
V2	stress_all	kmac_stress_all	4.421m	37.501ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.610s	29.371us	1	1	100.00
V2	alert_test	kmac_alert_test	1.690s	67.861us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.510s	149.357us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.510s	149.357us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.680s	51.916us	1	1	100.00
		kmac_csr_rw	1.820s	98.444us	1	1	100.00
		kmac_csr_aliasing	5.880s	135.089us	1	1	100.00
		kmac_same_csr_outstanding	2.680s	337.229us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.680s	51.916us	1	1	100.00
		kmac_csr_rw	1.820s	98.444us	1	1	100.00
		kmac_csr_aliasing	5.880s	135.089us	1	1	100.00
		kmac_same_csr_outstanding	2.680s	337.229us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.460s	293.847us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.460s	293.847us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.460s	293.847us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.460s	293.847us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.420s	85.578us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	34.630s	12.614ms	1	1	100.00
		kmac_tl_intg_err	3.750s	195.715us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.750s	195.715us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.750s	46.638us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.880s	461.903us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.779m	50.201ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.460s	293.847us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	34.630s	12.614ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	34.630s	12.614ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	34.630s	12.614ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.880s	461.903us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.750s	46.638us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	34.630s	12.614ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.092m	14.307ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.880s	461.903us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	17.890s	3.603ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.85051435257776078157022524164353936111458380300499615718847007134177025489146
      Line 94, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3603365544 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3603365544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---