645424b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 38.000s | 5.759ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 15.400us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 35.858us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 56.784us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 24.969us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 3.000s | 9.440us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 35.858us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 24.969us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 1.950m | 22.499ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 39.000s | 991.358us | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 23.000s | 541.463us | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 94.195us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 984.154ns | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 984.154ns | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 15.400us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 35.858us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 24.969us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 35.202us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 15.400us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 35.858us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 24.969us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 35.202us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 12.808us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 15.407us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_errors has 1 failures.
0.mbx_tl_errors.32875935389564845622268732403022970202327892993442867079977173583703774480351
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 984154 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xb009966c a_data = 0xd3179beb a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x64 a_opcode = PutPartialData a_user = 0x3243 d_data = 0x49e85d75 d_size = 0x1 d_param = 0x0 d_source = 0xb5 d_opcode = AccessAckData d_error = 0 d_user = 11010110001100 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 984154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.35599794013060266317925502892463319748245195975417375193476417999293652281139
Line 95, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 15407034 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x4cc7f184 a_data = 0xc910c653 a_mask = 0x6 a_size = 0x2 a_param = 0x0 a_source = 0x31 a_opcode = PutPartialData a_user = 0x2442c d_data = 0xb8aeb9fa d_size = 0x1 d_param = 0x0 d_source = 0x11 d_opcode = AccessAckData d_error = 0 d_user = 11011110110011 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 15407034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.38458579006550819243295927384675630423609177429402621655913330208957292575944
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 9439514 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x683bc2e0 a_data = 0x409cafcd a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x4a a_opcode = PutFullData a_user = 0x1a8ee d_data = 0xe784dea6 d_size = 0x1 d_param = 0x0 d_source = 0x4f d_opcode = AccessAckData d_error = 0 d_user = 1000111110111 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 9439514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---