OTBN Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	155.669us	1	1	100.00
V1	single_binary	otbn_single	10.000s	62.132us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	20.197us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	47.124us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	126.716us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	72.651us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	35.521us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	47.124us	1	1	100.00
		otbn_csr_aliasing	7.000s	72.651us	1	1	100.00
V1	mem_walk	otbn_mem_walk	14.000s	375.706us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	11.000s	357.579us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	25.000s	307.826us	1	1	100.00
V2	multi_error	otbn_multi_err	41.000s	339.599us	1	1	100.00
V2	back_to_back	otbn_multi	22.000s	135.977us	1	1	100.00
V2	stress_all	otbn_stress_all	1.017m	209.543us	1	1	100.00
V2	lc_escalation	otbn_escalate	10.000s	256.474us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	162.961us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	14.000s	88.220us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	19.755us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	30.470us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	521.776us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	521.776us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	20.197us	1	1	100.00
		otbn_csr_rw	6.000s	47.124us	1	1	100.00
		otbn_csr_aliasing	7.000s	72.651us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	15.764us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	20.197us	1	1	100.00
		otbn_csr_rw	6.000s	47.124us	1	1	100.00
		otbn_csr_aliasing	7.000s	72.651us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	15.764us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	17.470us	1	1	100.00
		otbn_dmem_err	10.000s	20.402us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	39.386us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	644.235us	1	1	100.00
		otbn_mac_bignum_acc_err	8.000s	287.403us	1	1	100.00
		otbn_urnd_err	10.000s	22.525us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	42.193us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	38.578us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	53.568us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
		otbn_tl_intg_err	20.000s	109.629us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	6.000s	87.383us	0	1	0.00
V2S	prim_fsm_check	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	155.669us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	10.000s	20.402us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	17.470us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	20.000s	109.629us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	10.000s	256.474us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	17.470us	1	1	100.00
		otbn_dmem_err	10.000s	20.402us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	162.961us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	42.193us	1	1	100.00
		otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	62.132us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	17.470us	1	1	100.00
		otbn_dmem_err	10.000s	20.402us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	162.961us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	42.193us	1	1	100.00
		otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	10.000s	256.474us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	17.470us	1	1	100.00
		otbn_dmem_err	10.000s	20.402us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	162.961us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	42.193us	1	1	100.00
		otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	62.132us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	71.802us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	50.312us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	25.000s	406.464us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	25.000s	406.464us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	22.211us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	185.450us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	19.051us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	19.051us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	13.815us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	62.132us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	62.132us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	62.132us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	22.000s	135.977us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	62.132us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	62.132us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	43.112us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	62.132us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.483m	1.294ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.850m	4.323ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			40	41	97.56

Failure Buckets

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:
  • Test otbn_passthru_mem_tl_intg_err has 1 failures.

    • 0.otbn_passthru_mem_tl_intg_err.51800902036694334421337146111997389441280238125570688185298576368726989222514
      Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @  87383422 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  87383422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---