ROM_CTRL/64KB Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.910s 560.626us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.850s 306.398us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.110s 1.073ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.450s 299.556us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.130s 894.037us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.900s 286.227us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.110s 1.073ms 1 1 100.00
rom_ctrl_csr_aliasing 7.130s 894.037us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.360s 213.073us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.790s 699.597us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.270s 229.137us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 29.150s 4.832ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.460s 399.045us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.970s 442.282us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.820s 384.075us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.820s 384.075us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.850s 306.398us 1 1 100.00
rom_ctrl_csr_rw 7.110s 1.073ms 1 1 100.00
rom_ctrl_csr_aliasing 7.130s 894.037us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.900s 2.009ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.850s 306.398us 1 1 100.00
rom_ctrl_csr_rw 7.110s 1.073ms 1 1 100.00
rom_ctrl_csr_aliasing 7.130s 894.037us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.900s 2.009ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 30.730s 8.634ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.193m 1.447ms 1 1 100.00
rom_ctrl_tl_intg_err 36.740s 2.316ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.193m 1.447ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.193m 1.447ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.193m 1.447ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.193m 1.447ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.910s 560.626us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.910s 560.626us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.910s 560.626us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 36.740s 2.316ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.460s 399.045us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.866m 17.656ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 30.730s 8.634ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.193m 1.447ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.331m 50.003ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00