RV_TIMER Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.470s	14.288us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.540s	13.120us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.740s	13.040us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.960s	133.236us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.590s	20.677us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.900s	25.915us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.740s	13.040us	1	1	100.00
		rv_timer_csr_aliasing	1.590s	20.677us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.550s	42.447us	1	1	100.00
V2	disabled	rv_timer_disabled	3.360s	2.252ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.444m	182.033ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.444m	182.033ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.710s	2.063ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.520s	13.225us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.590s	13.792us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.760s	217.354us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.760s	217.354us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.540s	13.120us	1	1	100.00
		rv_timer_csr_rw	1.740s	13.040us	1	1	100.00
		rv_timer_csr_aliasing	1.590s	20.677us	1	1	100.00
		rv_timer_same_csr_outstanding	1.530s	23.223us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.540s	13.120us	1	1	100.00
		rv_timer_csr_rw	1.740s	13.040us	1	1	100.00
		rv_timer_csr_aliasing	1.590s	20.677us	1	1	100.00
		rv_timer_same_csr_outstanding	1.530s	23.223us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.870s	179.143us	1	1	100.00
		rv_timer_tl_intg_err	1.850s	391.889us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.850s	391.889us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	12.230s	8.168ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.430s	14.753us	1	1	100.00
		rv_timer_max	1.400s	48.902us	1	1	100.00
		TOTAL			19	19	100.00