SPI_DEVICE/1R1W Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.341m	43.798ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.900s	188.817us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.930s	62.790us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.400s	1.205ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.690s	311.857us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.310s	55.483us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.930s	62.790us	1	1	100.00
		spi_device_csr_aliasing	15.690s	311.857us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.500s	13.990us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.630s	22.735us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.680s	18.494us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.750s	2.785us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.740s	5.916us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.990s	34.889us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.990s	34.889us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.580s	26.776us	1	1	100.00
		spi_device_tpm_sts_read	1.960s	125.844us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.520s	31.149us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.170s	4.516ms	1	1	100.00
		spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.360s	3.529ms	1	1	100.00
		spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.360s	3.529ms	1	1	100.00
		spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.900s	4.771ms	1	1	100.00
		spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.900s	4.771ms	1	1	100.00
		spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.900s	4.771ms	1	1	100.00
		spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.900s	4.771ms	1	1	100.00
		spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.900s	4.771ms	1	1	100.00
		spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.950s	25.822ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	24.640s	14.140ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	24.640s	14.140ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	24.640s	14.140ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.300s	358.294us	1	1	100.00
		spi_device_read_buffer_direct	4.600s	380.127us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	24.640s	14.140ms	1	1	100.00
		spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.800s	31.556us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.770s	175.114us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.770s	175.114us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.341m	43.798ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.630s	6.061ms	1	1	100.00
V2	stress_all	spi_device_stress_all	57.320s	25.608ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.660s	13.380us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.660s	17.667us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.490s	310.204us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.490s	310.204us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.900s	188.817us	1	1	100.00
		spi_device_csr_rw	2.930s	62.790us	1	1	100.00
		spi_device_csr_aliasing	15.690s	311.857us	1	1	100.00
		spi_device_same_csr_outstanding	3.880s	225.450us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.900s	188.817us	1	1	100.00
		spi_device_csr_rw	2.930s	62.790us	1	1	100.00
		spi_device_csr_aliasing	15.690s	311.857us	1	1	100.00
		spi_device_same_csr_outstanding	3.880s	225.450us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.080s	485.470us	1	1	100.00
		spi_device_tl_intg_err	6.480s	347.594us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.480s	347.594us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.828m	66.185ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.106230818640875078881943964027408865766194308534174556227940102274269851614166
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1539824 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[7])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1539824 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1539824 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[903])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.52800960142645905080653524448292628596091462670400276615754092537476426708926
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3559968 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe54457 [111001010100010001010111] vs 0x0 [0])
        UVM_ERROR @   3564968 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa292fe [101000101001001011111110] vs 0x0 [0])
        UVM_ERROR @   3657968 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb2b29 [10110010101100101001] vs 0x0 [0])
        UVM_ERROR @   3702968 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x43f45a [10000111111010001011010] vs 0x0 [0])
        UVM_ERROR @   3735968 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf7cc49 [111101111100110001001001] vs 0x0 [0])