SPI_HOST Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	14.000s	205.547us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	19.420us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	66.431us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	114.252us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	109.409us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	66.610us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	66.431us	1	1	100.00
		spi_host_csr_aliasing	4.000s	109.409us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	29.559us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	22.584us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	12.000s	34.753us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	11.000s	68.418us	1	1	100.00
		spi_host_error_cmd	10.000s	69.729us	1	1	100.00
		spi_host_event	1.983m	16.401ms	1	1	100.00
V2	clock_rate	spi_host_speed	16.000s	88.120us	1	1	100.00
V2	speed	spi_host_speed	16.000s	88.120us	1	1	100.00
V2	chip_select_timing	spi_host_speed	16.000s	88.120us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	15.000s	358.679us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	8.000s	36.079us	1	1	100.00
V2	cpol_cpha	spi_host_speed	16.000s	88.120us	1	1	100.00
V2	full_cycle	spi_host_speed	16.000s	88.120us	1	1	100.00
V2	duplex	spi_host_smoke	14.000s	205.547us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	14.000s	205.547us	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	37.646us	1	1	100.00
V2	spien	spi_host_spien	5.000s	311.809us	1	1	100.00
V2	stall	spi_host_status_stall	1.200m	7.611ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	6.000s	63.147us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	11.000s	68.418us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	178.604us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	19.682us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	87.759us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	87.759us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	19.420us	1	1	100.00
		spi_host_csr_rw	4.000s	66.431us	1	1	100.00
		spi_host_csr_aliasing	4.000s	109.409us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	70.546us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	19.420us	1	1	100.00
		spi_host_csr_rw	4.000s	66.431us	1	1	100.00
		spi_host_csr_aliasing	4.000s	109.409us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	70.546us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	444.130us	1	1	100.00
		spi_host_sec_cm	4.000s	85.687us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	444.130us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.917m	7.814ms	1	1	100.00
		TOTAL			26	26	100.00