SRAM_CTRL/MAIN Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.750s	513.090us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.720s	38.476us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.850s	23.949us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.240s	93.236us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.650s	44.328us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.800s	1.452ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.850s	23.949us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	44.328us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.585m	4.033ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.871m	4.594ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.913m	31.817ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.369m	7.279ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	22.064m	1.036s	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	17.576m	32.387ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.190s	1.669ms	1	1	100.00
V2	executable	sram_ctrl_executable	11.802m	25.286ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.053m	863.517us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.781m	6.641ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	22.110s	746.358us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	7.720s	1.432ms	1	1	100.00
		sram_ctrl_throughput_w_readback	27.060s	13.587ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.232m	13.757ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.740s	694.781us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	27.320m	211.944ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.930s	21.681us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.120s	255.202us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.120s	255.202us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.720s	38.476us	1	1	100.00
		sram_ctrl_csr_rw	1.850s	23.949us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	44.328us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.250s	37.893us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.720s	38.476us	1	1	100.00
		sram_ctrl_csr_rw	1.850s	23.949us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	44.328us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.250s	37.893us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.650s	14.729ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.780s	2.252us	0	1	0.00
		sram_ctrl_tl_intg_err	2.650s	125.295us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.780s	2.252us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.650s	125.295us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.232m	13.757ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.232m	13.757ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.850s	23.949us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	11.802m	25.286ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	11.802m	25.286ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	11.802m	25.286ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.190s	1.669ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	7.540s	1.251ms	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.650s	14.729ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.740s	680.319us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.750s	513.090us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.750s	513.090us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	11.802m	25.286ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.780s	2.252us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.190s	1.669ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.780s	2.252us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.780s	2.252us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.750s	513.090us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.780s	2.252us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.100m	2.021ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.37972285370039258170453136472963921177301540362030855305318959036558612611837
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1251303271 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1251303271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.92590952074791618884007623959312639758647985673006161084152661243131041732884
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2251614 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2251614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---