UART Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.150s	269.891us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.520s	47.707us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.660s	13.177us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.870s	434.861us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.630s	35.094us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.610s	27.922us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.660s	13.177us	1	1	100.00
		uart_csr_aliasing	1.630s	35.094us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	2.014m	168.102ms	1	1	100.00
V2	parity	uart_smoke	2.150s	269.891us	1	1	100.00
		uart_tx_rx	2.014m	168.102ms	1	1	100.00
V2	parity_error	uart_intr	1.081m	52.963ms	1	1	100.00
		uart_rx_parity_err	36.180s	244.196ms	1	1	100.00
V2	watermark	uart_tx_rx	2.014m	168.102ms	1	1	100.00
		uart_intr	1.081m	52.963ms	1	1	100.00
V2	fifo_full	uart_fifo_full	3.365m	172.675ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	2.233m	132.237ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	24.390s	35.002ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.081m	52.963ms	1	1	100.00
V2	rx_break_err	uart_intr	1.081m	52.963ms	1	1	100.00
V2	rx_timeout	uart_intr	1.081m	52.963ms	1	1	100.00
V2	perf	uart_perf	45.290s	10.875ms	1	1	100.00
V2	sys_loopback	uart_loopback	13.100s	7.792ms	1	1	100.00
V2	line_loopback	uart_loopback	13.100s	7.792ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.361m	150.761ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.110s	5.098ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.840s	1.363ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.340s	3.907ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.290m	55.167ms	1	1	100.00
V2	stress_all	uart_stress_all	2.823m	90.916ms	1	1	100.00
V2	alert_test	uart_alert_test	1.540s	42.853us	1	1	100.00
V2	intr_test	uart_intr_test	1.580s	51.384us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.270s	50.225us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.270s	50.225us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.520s	47.707us	1	1	100.00
		uart_csr_rw	1.660s	13.177us	1	1	100.00
		uart_csr_aliasing	1.630s	35.094us	1	1	100.00
		uart_same_csr_outstanding	1.750s	111.461us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.520s	47.707us	1	1	100.00
		uart_csr_rw	1.660s	13.177us	1	1	100.00
		uart_csr_aliasing	1.630s	35.094us	1	1	100.00
		uart_same_csr_outstanding	1.750s	111.461us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	2.290s	304.043us	1	1	100.00
		uart_tl_intg_err	1.990s	48.165us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.990s	48.165us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.350s	2.058ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00