CHIP Simulation Results

Wednesday May 28 2025 17:00:46 UTC

GitHub Revision: `645424b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.494m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.494m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	53.787s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	40.521s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	24.829s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.326m	6.613ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.326m	6.613ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.326m	6.613ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	39.530s	10.240us	0	1	0.00
		chip_sw_example_manufacturer	2.935m		0	1	0.00
		chip_sw_example_concurrency	3.841m	5.258ms	1	1	100.00
		chip_sw_uart_smoketest_signed	10.569s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	14.290s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	13.020s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	13.020s		0	1	0.00
V1	xbar_smoke	xbar_smoke	10.530s	12.643us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.242m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.921m	8.756ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.627m	4.652ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	16.742s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	19.233s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.947s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	17.456s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.610s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.610s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.879m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.135m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.211m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.211m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.535m	5.119ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.631m	3.244ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.810m	14.811ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.557s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.020s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.131m	16.044ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.580m	4.918ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	19.309m	18.020ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	19.309m	18.020ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.622s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.522m	3.768ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.522m	3.768ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.511m	18.025ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.418m	5.500ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.408m	5.288ms	1	1	100.00
		chip_sw_aes_idle	3.777m	4.587ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.257m	5.323ms	1	1	100.00
		chip_sw_kmac_idle	4.599m	4.983ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.346m	11.868ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	11.162m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.990m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.245m	12.016ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	15.617s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.176s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.447s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.604s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.288s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.673s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.444s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.617s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.176s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.447s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.604s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.288s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.673s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.444s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.006s		0	1	0.00
		chip_sw_aes_enc_jitter_en	52.780s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.570s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.890s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	46.100s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.129s		0	1	0.00
		chip_sw_clkmgr_jitter	4.821m	5.455ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.511m	5.314ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.026s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	49.130s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	48.950s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	56.480s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	49.140s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	45.850s	10.280us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.171s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.934s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.570s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.116s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.042m	13.795ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.608m	13.783ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.522m	3.768ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.758s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.608m	13.783ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	17.591s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	16.134s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	24.437s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	17.971s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	16.229s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.042m	13.795ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.810m	14.811ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.288m	20.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.494m	8.785ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.154m	7.917ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.556m	3.585ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.042m	13.795ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.474s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.591s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.042m	13.795ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.050s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.154m	7.917ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.316s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.764s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.291s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.536s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.872s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.919s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.591s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.232s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	22.318s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.232s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.232s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.232s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.411m	10.319ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.436s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.361s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.955s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.372s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.232s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.461m	7.093ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.650m	13.568ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.966s		0	1	0.00
		chip_prim_tl_access	17.419m	20.798ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.617s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.176s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.447s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.604s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.288s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.673s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.444s		0	1	0.00
		chip_rv_dm_lc_disabled	9.131m	16.044ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.900m	3.682ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	52.780s	10.140us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.224m	4.698ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.777m	4.587ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.230m	3.467ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	47.570s	10.240us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.257m	5.323ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.603m	4.549ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.527m	5.007ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	46.100s	10.360us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.461m	7.093ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.232s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	43.750s	10.340us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.320m	6.375ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.599m	4.983ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.919s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.919s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.563s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.711m	4.786ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	15.569s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.461m	7.093ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.890s	10.320us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.732s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.006s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.408m	5.288ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.408m	5.288ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.408m	5.288ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.675m	4.933ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.650m	13.568ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.650m	13.568ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.455m	7.149ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.129s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.966s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.042m	13.795ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.211m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.232s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	6.675m	4.933ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.461m	7.093ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.455m	7.149ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.242m	5.442ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	6.675m	4.933ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.461m	7.093ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.455m	7.149ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.242m	5.442ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.232s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.268s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	22.318s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.436s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.361s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.955s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.372s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.232s		0	1	0.00
		chip_prim_tl_access	17.419m	20.798ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	17.419m	20.798ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.408s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.232s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.934s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.006s		0	1	0.00
		chip_sw_aes_enc_jitter_en	52.780s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.570s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.890s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	46.100s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.129s		0	1	0.00
		chip_sw_clkmgr_jitter	4.821m	5.455ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.291m	9.339ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.291m	9.339ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.500m	5.530ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.479m	4.048ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.664m	3.653ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.672m	6.074ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.272m	4.547ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.150m	4.045ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.242m	5.442ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.288m	20.017ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.288m	20.017ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.990m	3.766ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.069m	4.266ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.683m	4.467ms	1	1	100.00
		chip_sw_csrng_smoketest	3.005m	4.886ms	1	1	100.00
		chip_sw_gpio_smoketest	4.014m	4.835ms	1	1	100.00
		chip_sw_hmac_smoketest	4.048m	5.028ms	1	1	100.00
		chip_sw_kmac_smoketest	4.252m	4.410ms	1	1	100.00
		chip_sw_otbn_smoketest	4.967m	5.810ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.490m	3.344ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.870m	4.785ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.252m	4.741ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.211m	5.028ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.225m	3.328ms	1	1	100.00
		chip_sw_uart_smoketest	3.285m	4.350ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	15.031s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	10.569s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.242m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.038s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.812m	4.838ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.839m	4.526ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.588m	6.214ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.382m	5.076ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.240s		0	1	0.00
		chip_rv_dm_lc_disabled	9.131m	16.044ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	25.191s		0	1	0.00
		chip_sw_lc_walkthrough_prod	16.460s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.399s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.398s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.240s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.376s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.381s		0	1	0.00
		rom_volatile_raw_unlock	11.427s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.641s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.119m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.016m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.865m	5.185ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.865m	5.185ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	13.020s		0	1	0.00
		chip_same_csr_outstanding	9.790s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	13.020s		0	1	0.00
		chip_same_csr_outstanding	9.790s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.403m	241.545us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.660s	12.477us	1	1	100.00
		xbar_smoke_large_delays	4.055m	2.179ms	1	1	100.00
		xbar_smoke_slow_rsp	6.076m	2.252ms	1	1	100.00
		xbar_random_zero_delays	57.470s	53.141us	1	1	100.00
		xbar_random_large_delays	11.733m	5.969ms	1	1	100.00
		xbar_random_slow_rsp	29.596m	11.341ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.756m	207.642us	1	1	100.00
		xbar_error_and_unmapped_addr	59.720s	144.787us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	39.430s	125.742us	1	1	100.00
		xbar_error_and_unmapped_addr	59.720s	144.787us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.612m	427.655us	1	1	100.00
		xbar_access_same_device_slow_rsp	50.789m	20.434ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	14.860s	37.125us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.033m	297.443us	1	1	100.00
		xbar_stress_all_with_error	3.805m	245.359us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.837m	158.387us	1	1	100.00
		xbar_stress_all_with_reset_error	10.468m	1.688ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.607s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.259s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.679s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	15.086s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.639s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	15.678s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.799s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	14.683s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.731s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.484s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.350s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.847s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.640s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.260s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.220s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.665s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.741s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.077s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.373s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.412s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.159s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.828s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.341s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.898s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.950s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.228s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.279s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.851s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.016s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.470s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.827s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.912s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.948s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.701s		0	1	0.00
		rom_e2e_asm_init_dev	11.412s		0	1	0.00
		rom_e2e_asm_init_prod	12.142s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.056s		0	1	0.00
		rom_e2e_asm_init_rma	12.107s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.756s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.696s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.002s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.438s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.332m	4.474ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.542m	4.256ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.060s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.659s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.831s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.781s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.042m	13.795ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.284s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.708m	15.573ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.023s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.721s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.060s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.659s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.831s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.065s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.141s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.735s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	56.205s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.202m	13.109ms	1	1	100.00
		chip_plic_all_irqs_0	9.506m	6.430ms	1	1	100.00
		chip_plic_all_irqs_10	8.899m	6.138ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.433m	4.333ms	1	1	100.00
		chip_sw_dma_abort	4.522m	3.973ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.959s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.822s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.269s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.795s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.925s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.614s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.382s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.468s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.742s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.898s		0	1	0.00
		chip_sw_mbx_smoketest	3.982m	5.725ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.6749681435767722424669638100558973877277216022356492132029672475965050554433
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (a5a9dd)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 158.741s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.1413152879074077184212125692779885798508494755243428588727455721849622616730
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (1a55f2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 120.657s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.42883669758067469792984428510235416922600812167644570619243939922785019949669
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (75eee8)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 102.707s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.88772333980621688841874717021172919690506370198275376376429413067833981679346
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (c5af08)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 118.184s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.79695602261523891172259797133983321164585509946627375994203573576347124245086
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (747120)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 79.831s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.22863833927300118835977072069357080630381571170711402430603639346266859445334
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.61835961867873594564037012463947719383315222742817958867625883876512530233633
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.91123845427762584473857195320759248753682100527798336489730992600972312833100
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.102786436771550005978562032793747887181906918691104006732010671880792863456779
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.41122295871518347037992576364079044464806297136699301804698270270680659641983
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.1859433343593093254998463360720905462318264151862225488743295556306918532796
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.56702629114765667112828219167770333677976205567536015734397756247420677936447
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.104487729848485945082649401351132405190622847814925736280583793047883580376492
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.50906610081695774215239161975485732197875569256602905354158040560811467333289
Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.610278 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.610278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.61382372152286246013347962572087000936627463379975795286437923319282203779824
Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18019.523087 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18019.523087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.9835557186810178316089024314667846467599737425307193033191139794672601075342
Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18024.963232 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18024.963232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.51962663123137656042051177061875920939386412403317236215882511418008734773991
Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.549702 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.549702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.21625499650140449013647080703985496416179241120732519539105854507359608284780
Line 444, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12019.415230 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12019.415230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.56253010056973045169029895595787145830717762430878280175708434131290554722815
Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12015.809858 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.809858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.9571179800220078537925603917600699273663703063523832078680048953004399902317
Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7092.713266 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (92307463728629059120858826594393819774419359519768990696854124950263344974268 [0xcc142c4a2a766e684286aa41f603d16d7e8a90e145fd92451c66f7aa45dcc9bc] vs 15556428662618138674103001404750890903751441619819542583076194220608656845702 [0x2264a068c7f854883d34cdee8b54bce9a282379786bf6cd9d9df5e98d91d2b86])
  UVM_INFO @ 7092.713266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.34241757609306183272289553459560552096018640456588570577794624906226744854592
Line 474, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 10318.878120 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (40551494561341060674375783641720234725920533224404100188102905790171218324693 [0x59a75522770629be6880c54b74978aaea785b47caa55276c815293fbc7da2cd5] vs 17706344462052377709100809709640547410639185720146153746633548134973412476198 [0x27256f91d92d5c7edaab3e91e7cc24d0d0154951c3ecd565956aca6dd8bc0526])
  UVM_INFO @ 10318.878120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.88651077048869322256126235929525840981860105074297981553925097941285678413755
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 5119.410975 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h47203d8e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3b  a_opcode: 'h0  a_user: 'h26902  d_param: 'h0  d_source: 'h3b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5119.410975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.20114032458263217609885540573475857510309431846188192364621428108677580694291
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3243.634547 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h1d521dc4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h1  a_user: 'h248e7  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3243.634547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.2279398849223171905225657015248083186657847960060627208700753731008834460024
    Line 604, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.80435582755862420134592624328798092332803301188507282389579266832581875420926
    Line 514, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4652.045010 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4652.045010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.96156724725996335860534916777071824413290317126425266432807224174805621382855
    Line 681, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 7916.797496 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 7916.797496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.55617057340432822403206110715397983582742136999779558545885966490633004823451
    Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5530.234120 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5530.234120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.41470572700359234235302591117983826080269150300263603930046738617169262525670
    Line 438, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4047.831190 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4047.831190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.109999012473742989357756890367732360802955273797832618827269708708301403885651
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3768.231408 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3768.231408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.114260020843517278723700752381685534550298872687374073668701884361683134873271
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6073.697984 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6073.697984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.60433453597649066439397054640047153288910691183172917330946716949587077909229
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.110877080235685579363730428726879038665254734354926971046834274237145706528426
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5184.911204 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5184.911204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.5212834127016003671179672895704167289767815610196739486127769407717018439052
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14810.871746 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14810.871746 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.24764050971093871472713068430648479026523986466844886080125757464725942522979
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.42876164773592251328307513732275606687629021366542873120590564100110534940336
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3973.444602 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3973.444602 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```