DMA Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.878ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	2.357ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	9.000s	666.261us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	20.261us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	32.424us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	8.000s	157.421us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	440.933us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	30.159us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	32.424us	1	1	100.00
		dma_csr_aliasing	9.000s	440.933us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	48.000s	13.003ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	30.517m	393.478ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	9.767m	44.058ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.700m	29.366ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	30.517m	393.478ms	1	1	100.00
V2	dma_abort	dma_abort	8.000s	383.963us	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.533m	24.782ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	24.260us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	117.396us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	117.396us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	20.261us	1	1	100.00
		dma_csr_rw	4.000s	32.424us	1	1	100.00
		dma_csr_aliasing	9.000s	440.933us	1	1	100.00
		dma_same_csr_outstanding	5.000s	278.763us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	20.261us	1	1	100.00
		dma_csr_rw	4.000s	32.424us	1	1	100.00
		dma_csr_aliasing	9.000s	440.933us	1	1	100.00
		dma_same_csr_outstanding	5.000s	278.763us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	26.000s	72.581us	1	1	100.00
		dma_generic_stress	2.700m	29.366ms	1	1	100.00
		dma_handshake_stress	30.517m	393.478ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	197.656us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.467m	39.405ms	1	1	100.00
		dma_longer_transfer	5.000s	95.288us	1	1	100.00
		TOTAL			21	21	100.00