EDN Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.840s	17.975us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.750s	17.063us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.660s	82.030us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.300s	511.138us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.900s	29.094us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.560s	40.855us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.660s	82.030us	1	1	100.00
		edn_csr_aliasing	1.900s	29.094us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	3.000s	192.372us	1	1	100.00
V2	csrng_commands	edn_genbits	3.000s	192.372us	1	1	100.00
V2	genbits	edn_genbits	3.000s	192.372us	1	1	100.00
V2	interrupts	edn_intr	1.810s	21.155us	1	1	100.00
V2	alerts	edn_alert	2.010s	45.486us	1	1	100.00
V2	errs	edn_err	1.730s	21.376us	1	1	100.00
V2	disable	edn_disable	1.700s	12.864us	1	1	100.00
		edn_disable_auto_req_mode	1.700s	73.924us	1	1	100.00
V2	stress_all	edn_stress_all	3.650s	303.395us	1	1	100.00
V2	intr_test	edn_intr_test	1.660s	142.398us	1	1	100.00
V2	alert_test	edn_alert_test	1.860s	33.016us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.650s	60.291us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.650s	60.291us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.750s	17.063us	1	1	100.00
		edn_csr_rw	1.660s	82.030us	1	1	100.00
		edn_csr_aliasing	1.900s	29.094us	1	1	100.00
		edn_same_csr_outstanding	1.940s	33.021us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.750s	17.063us	1	1	100.00
		edn_csr_rw	1.660s	82.030us	1	1	100.00
		edn_csr_aliasing	1.900s	29.094us	1	1	100.00
		edn_same_csr_outstanding	1.940s	33.021us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	7.640s	989.644us	1	1	100.00
		edn_tl_intg_err	2.180s	98.314us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.690s	19.067us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.010s	45.486us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.640s	989.644us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.640s	989.644us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.640s	989.644us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.640s	989.644us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.010s	45.486us	1	1	100.00
		edn_sec_cm	7.640s	989.644us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.010s	45.486us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.180s	98.314us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.105m	8.192ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00