HMAC Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.840s 1.142ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.560s 13.437us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.510s 80.775us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.440s 219.646us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.050s 294.424us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.940s 22.104us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.510s 80.775us 1 1 100.00
hmac_csr_aliasing 3.050s 294.424us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 38.540s 7.426ms 1 1 100.00
V2 back_pressure hmac_back_pressure 36.310s 1.831ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.630s 169.979us 1 1 100.00
hmac_test_sha384_vectors 5.820m 22.619ms 1 1 100.00
hmac_test_sha512_vectors 5.915m 19.717ms 1 1 100.00
hmac_test_hmac256_vectors 7.330s 212.174us 1 1 100.00
hmac_test_hmac384_vectors 12.230s 1.177ms 1 1 100.00
hmac_test_hmac512_vectors 11.280s 1.060ms 1 1 100.00
V2 burst_wr hmac_burst_wr 2.660s 639.850us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.291m 6.299ms 1 1 100.00
V2 error hmac_error 16.460s 10.001ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 21.530s 10.099ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.840s 1.142ms 1 1 100.00
hmac_long_msg 38.540s 7.426ms 1 1 100.00
hmac_back_pressure 36.310s 1.831ms 1 1 100.00
hmac_datapath_stress 5.291m 6.299ms 1 1 100.00
hmac_burst_wr 2.660s 639.850us 1 1 100.00
hmac_stress_all 16.778m 103.597ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.840s 1.142ms 1 1 100.00
hmac_long_msg 38.540s 7.426ms 1 1 100.00
hmac_back_pressure 36.310s 1.831ms 1 1 100.00
hmac_datapath_stress 5.291m 6.299ms 1 1 100.00
hmac_wipe_secret 21.530s 10.099ms 1 1 100.00
hmac_test_sha256_vectors 8.630s 169.979us 1 1 100.00
hmac_test_sha384_vectors 5.820m 22.619ms 1 1 100.00
hmac_test_sha512_vectors 5.915m 19.717ms 1 1 100.00
hmac_test_hmac256_vectors 7.330s 212.174us 1 1 100.00
hmac_test_hmac384_vectors 12.230s 1.177ms 1 1 100.00
hmac_test_hmac512_vectors 11.280s 1.060ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.840s 1.142ms 1 1 100.00
hmac_long_msg 38.540s 7.426ms 1 1 100.00
hmac_back_pressure 36.310s 1.831ms 1 1 100.00
hmac_datapath_stress 5.291m 6.299ms 1 1 100.00
hmac_burst_wr 2.660s 639.850us 1 1 100.00
hmac_error 16.460s 10.001ms 1 1 100.00
hmac_wipe_secret 21.530s 10.099ms 1 1 100.00
hmac_test_sha256_vectors 8.630s 169.979us 1 1 100.00
hmac_test_sha384_vectors 5.820m 22.619ms 1 1 100.00
hmac_test_sha512_vectors 5.915m 19.717ms 1 1 100.00
hmac_test_hmac256_vectors 7.330s 212.174us 1 1 100.00
hmac_test_hmac384_vectors 12.230s 1.177ms 1 1 100.00
hmac_test_hmac512_vectors 11.280s 1.060ms 1 1 100.00
hmac_stress_all 16.778m 103.597ms 1 1 100.00
V2 stress_all hmac_stress_all 16.778m 103.597ms 1 1 100.00
V2 alert_test hmac_alert_test 1.570s 45.867us 1 1 100.00
V2 intr_test hmac_intr_test 1.450s 11.934us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.100s 247.831us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.100s 247.831us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.560s 13.437us 1 1 100.00
hmac_csr_rw 1.510s 80.775us 1 1 100.00
hmac_csr_aliasing 3.050s 294.424us 1 1 100.00
hmac_same_csr_outstanding 1.880s 85.659us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.560s 13.437us 1 1 100.00
hmac_csr_rw 1.510s 80.775us 1 1 100.00
hmac_csr_aliasing 3.050s 294.424us 1 1 100.00
hmac_same_csr_outstanding 1.880s 85.659us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.860s 106.572us 1 1 100.00
hmac_tl_intg_err 2.530s 354.118us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.530s 354.118us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.840s 1.142ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.560s 225.749us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 14.050s 2.077ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.800s 21.604us 1 1 100.00
TOTAL 28 28 100.00