I2C Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: `5c5f5a8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	58.520s	1.859ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	11.590s	986.903us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.760s	25.123us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.610s	19.746us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.420s	366.254us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.810s	449.896us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.630s	40.934us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.610s	19.746us	1	1	100.00
		i2c_csr_aliasing	1.810s	449.896us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	10.210s	391.619us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	5.575m	48.629ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.042m	24.375ms	1	1	100.00
V2	host_override	i2c_host_override	1.650s	26.104us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.310m	14.237ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.190m	6.716ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.660s	339.063us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.460s	1.231ms	1	1	100.00
		i2c_host_fifo_reset_rx	6.850s	263.280us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.822m	13.874ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.110s	1.903ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.120s	392.216us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.140s	7.433ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	18.020s	18.078ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.220s	7.886ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	45.580s	1.482ms	1	1	100.00
		i2c_target_intr_smoke	4.890s	1.102ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.270s	277.274us	1	1	100.00
		i2c_target_fifo_reset_tx	2.430s	400.833us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	7.314m	70.024ms	1	1	100.00
		i2c_target_stress_rd	45.580s	1.482ms	1	1	100.00
		i2c_target_intr_stress_wr	9.940s	10.498ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.930s	4.406ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	9.400s	3.320ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.450s	1.054ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	5.320s	11.775ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.650s	479.738us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.420s	832.746us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.042m	24.375ms	1	1	100.00
		i2c_host_perf_precise	1.193m	25.173ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.110s	1.903ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	7.810s	452.688us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.860s	608.585us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.790s	1.003ms	1	1	100.00
		i2c_target_nack_txstretch	2.650s	140.941us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	21.980s	5.364ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.700s	2.776ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.770s	19.762us	1	1	100.00
V2	intr_test	i2c_intr_test	1.670s	19.960us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.340s	174.721us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.340s	174.721us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.760s	25.123us	1	1	100.00
		i2c_csr_rw	1.610s	19.746us	1	1	100.00
		i2c_csr_aliasing	1.810s	449.896us	1	1	100.00
		i2c_same_csr_outstanding	1.980s	62.641us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.760s	25.123us	1	1	100.00
		i2c_csr_rw	1.610s	19.746us	1	1	100.00
		i2c_csr_aliasing	1.810s	449.896us	1	1	100.00
		i2c_same_csr_outstanding	1.980s	62.641us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.500s	105.183us	1	1	100.00
		i2c_sec_cm	1.680s	175.523us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.500s	105.183us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.030s	2.321ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.130s	40.704us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	18.220s	697.904us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.72444219655914221613382129814659413372511899369314436040203651124005556958258
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2321392888 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2321392888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.72453922094648767646292715839172350416304402827274430956414040746575120196707
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 697904399 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 697904399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.8632038889946407735388725661282575352551950012450058970090278191157841085435
Line 127, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 48629197423 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3768670

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.23859501783079217329275567118173302873399636806071432217391499354939077945972
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  40704484 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 25 [0x19])
  UVM_INFO @  40704484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.96043497650040744523003271752832462310906784150085482617264671387760371053498
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 11774935424 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 11774935424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.38370265694461251786954158640972464486097123217227228051116209311732636762032
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```