KEYMGR Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.710s	902.503us	1	1	100.00
V1	random	keymgr_random	24.880s	3.819ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.860s	192.341us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.750s	9.253us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.790s	641.541us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	3.580s	829.852us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.420s	157.376us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.750s	9.253us	0	1	0.00
		keymgr_csr_aliasing	3.580s	829.852us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	29.620s	855.087us	1	1	100.00
V2	sideload	keymgr_sideload	3.970s	366.795us	1	1	100.00
		keymgr_sideload_kmac	2.820s	56.279us	1	1	100.00
		keymgr_sideload_aes	2.580s	125.879us	1	1	100.00
		keymgr_sideload_otbn	4.910s	252.384us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	7.390s	430.580us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.570s	554.684us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.540s	141.867us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.580s	347.071us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.430s	447.412us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	6.900s	270.142us	1	1	100.00
V2	stress_all	keymgr_stress_all	13.220s	2.524ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.500s	10.844us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.460s	10.499us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.760s	136.210us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.760s	136.210us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.860s	192.341us	1	1	100.00
		keymgr_csr_rw	1.750s	9.253us	0	1	0.00
		keymgr_csr_aliasing	3.580s	829.852us	1	1	100.00
		keymgr_same_csr_outstanding	2.400s	47.797us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.860s	192.341us	1	1	100.00
		keymgr_csr_rw	1.750s	9.253us	0	1	0.00
		keymgr_csr_aliasing	3.580s	829.852us	1	1	100.00
		keymgr_same_csr_outstanding	2.400s	47.797us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
		keymgr_tl_intg_err	5.500s	797.286us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.950s	174.565us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.950s	174.565us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.950s	174.565us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.950s	174.565us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.950s	245.240us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.500s	797.286us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.950s	174.565us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	29.620s	855.087us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	24.880s	3.819ms	1	1	100.00
		keymgr_csr_rw	1.750s	9.253us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	24.880s	3.819ms	1	1	100.00
		keymgr_csr_rw	1.750s	9.253us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	24.880s	3.819ms	1	1	100.00
		keymgr_csr_rw	1.750s	9.253us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.570s	554.684us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.430s	447.412us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.430s	447.412us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	24.880s	3.819ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.720s	110.753us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.970s	689.104us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.570s	554.684us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.970s	689.104us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.970s	689.104us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.970s	689.104us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.880s	295.262us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.970s	689.104us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.050s	438.934us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.67204900215140554317802601385930177127099399636392636427857794568417130592537
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
        UVM_ERROR @   9253392 ps: (keymgr_csr_assert_fpv.sv:414) [ASSERT FAILED] sealing_sw_binding_4_rd_A
        UVM_INFO @   9253392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.57583976934001343098885769478733038044431494894150932975189381481084020857270
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @ 641540893 ps: (keymgr_csr_assert_fpv.sv:409) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @ 641540893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---