KMAC/MASKED Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	17.630s	9.458ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.630s	37.719us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.700s	92.382us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.300s	1.040ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.120s	790.573us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.890s	167.717us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.700s	92.382us	1	1	100.00
		kmac_csr_aliasing	7.120s	790.573us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.520s	14.891us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.770s	51.905us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	23.427m	48.011ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.690m	5.873ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.389m	523.123ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.880s	8.023ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.001m	238.371ms	1	1	100.00
		kmac_test_vectors_sha3_512	17.522m	41.301ms	1	1	100.00
		kmac_test_vectors_shake_128	36.317m	435.260ms	1	1	100.00
		kmac_test_vectors_shake_256	28.771m	81.788ms	1	1	100.00
		kmac_test_vectors_kmac	3.300s	413.946us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.500s	165.408us	1	1	100.00
V2	sideload	kmac_sideload	1.650m	103.268ms	1	1	100.00
V2	app	kmac_app	2.823m	4.405ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.477m	32.573ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.345m	14.846ms	1	1	100.00
V2	error	kmac_error	4.291m	34.689ms	1	1	100.00
V2	key_error	kmac_key_error	5.890s	1.074ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.600s	277.814us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.040s	42.393us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.630s	154.553us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	48.880s	20.488ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	3.220s	46.548us	1	1	100.00
V2	stress_all	kmac_stress_all	4.436m	22.160ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.520s	11.864us	1	1	100.00
V2	alert_test	kmac_alert_test	1.690s	39.879us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.830s	45.326us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.830s	45.326us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.630s	37.719us	1	1	100.00
		kmac_csr_rw	1.700s	92.382us	1	1	100.00
		kmac_csr_aliasing	7.120s	790.573us	1	1	100.00
		kmac_same_csr_outstanding	2.530s	71.810us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.630s	37.719us	1	1	100.00
		kmac_csr_rw	1.700s	92.382us	1	1	100.00
		kmac_csr_aliasing	7.120s	790.573us	1	1	100.00
		kmac_same_csr_outstanding	2.530s	71.810us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.870s	87.311us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.870s	87.311us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.870s	87.311us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.870s	87.311us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.630s	196.165us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	51.840s	18.835ms	1	1	100.00
		kmac_tl_intg_err	4.200s	838.211us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.200s	838.211us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	3.220s	46.548us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	17.630s	9.458ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.650m	103.268ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.870s	87.311us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	51.840s	18.835ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	51.840s	18.835ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	51.840s	18.835ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	17.630s	9.458ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	3.220s	46.548us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	51.840s	18.835ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.975m	13.340ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	17.630s	9.458ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.700s	58.143ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.77536121088597994525217707682541049350674319802586115635257666014016294523758
      Line 174, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58143118002 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 58143118002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---