KMAC/UNMASKED Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	26.700s	3.111ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.730s	52.318us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.640s	16.487us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.030s	10.307ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.830s	714.172us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.210s	216.710us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.640s	16.487us	1	1	100.00
		kmac_csr_aliasing	5.830s	714.172us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.620s	24.406us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.280s	27.557us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	4.124m	14.235ms	1	1	100.00
V2	burst_write	kmac_burst_write	39.310s	650.013us	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	18.326m	17.493ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.320s	591.564us	1	1	100.00
		kmac_test_vectors_sha3_384	20.650s	1.678ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.985m	33.239ms	1	1	100.00
		kmac_test_vectors_shake_128	1.562m	4.349ms	1	1	100.00
		kmac_test_vectors_shake_256	3.325m	10.784ms	1	1	100.00
		kmac_test_vectors_kmac	2.880s	114.860us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.870s	349.478us	1	1	100.00
V2	sideload	kmac_sideload	32.260s	2.410ms	1	1	100.00
V2	app	kmac_app	2.479m	17.617ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.958m	36.918ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	13.900s	341.211us	1	1	100.00
V2	error	kmac_error	2.117m	30.247ms	1	1	100.00
V2	key_error	kmac_key_error	5.450s	6.602ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.305m	10.038ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	23.740s	848.300us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	28.470s	2.978ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	29.480s	4.031ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.130s	90.277us	1	1	100.00
V2	stress_all	kmac_stress_all	1.914m	33.630ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.520s	14.301us	1	1	100.00
V2	alert_test	kmac_alert_test	1.580s	17.050us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.790s	260.605us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.790s	260.605us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.730s	52.318us	1	1	100.00
		kmac_csr_rw	1.640s	16.487us	1	1	100.00
		kmac_csr_aliasing	5.830s	714.172us	1	1	100.00
		kmac_same_csr_outstanding	2.080s	82.407us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.730s	52.318us	1	1	100.00
		kmac_csr_rw	1.640s	16.487us	1	1	100.00
		kmac_csr_aliasing	5.830s	714.172us	1	1	100.00
		kmac_same_csr_outstanding	2.080s	82.407us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.110s	469.808us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.110s	469.808us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.110s	469.808us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.110s	469.808us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.710s	25.467us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	19.530s	9.127ms	1	1	100.00
		kmac_tl_intg_err	2.790s	106.956us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.790s	106.956us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.130s	90.277us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	26.700s	3.111ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	32.260s	2.410ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.110s	469.808us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	19.530s	9.127ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	19.530s	9.127ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	19.530s	9.127ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	26.700s	3.111ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.130s	90.277us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	19.530s	9.127ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.288m	112.820ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	26.700s	3.111ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.870s	2.985ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.42287901456568401623009870486642482658217258935038824348881862805423327199353
      Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10038453157 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x26d8f000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10038453157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.44814352688022777971350927213987321664684952350363290295442339398377898384025
      Line 193, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2984543913 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2984543913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.13728621371627666639021140879344892090306225397307435376815917358265494182249
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
        UVM_ERROR @  25467032 ps: (kmac_csr_assert_fpv.sv:520) [ASSERT FAILED] prefix_5_rd_A
        UVM_INFO @  25467032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---