5c5f5a8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 29.000s | 664.800us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 3.000s | 83.183us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 23.229us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 55.486us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 27.604us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 4.852us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 23.229us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 27.604us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 16.000s | 2.451ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 32.000s | 2.772ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 27.000s | 2.776ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 3.000s | 49.384us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 4.937us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 4.937us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 3.000s | 83.183us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 23.229us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 27.604us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 41.711us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 3.000s | 83.183us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 23.229us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 27.604us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 41.711us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 34.575us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 9.220us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_errors has 1 failures.
0.mbx_tl_errors.33424257044408859060093490058984812229790793977632381989325229521797813704925
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 4937417 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x2a44a6a4 a_data = 0xfb9dec76 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x29 a_opcode = PutFullData a_user = 0x39fb1 d_data = 0x8c22784 d_size = 0x0 d_param = 0x0 d_source = 0x77 d_opcode = AccessAck d_error = 0 d_user = 11000011101100 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4937417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.75352444301337620908219737715073059795524521659667282361906216749941168963795
Line 88, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 9219748 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x881c7b2e a_data = 0x7b908711 a_mask = 0x4 a_size = 0x0 a_param = 0x0 a_source = 0x8c a_opcode = PutFullData a_user = 0x27755 d_data = 0xa3a9c7bd d_size = 0x1 d_param = 0x0 d_source = 0x7f d_opcode = AccessAck d_error = 0 d_user = 10100110001100 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 9219748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.23481729463958163265506342226725924995754525222442365955820297522413939459116
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 4851824 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x1a0f9a58 a_data = 0x1aee1175 a_mask = 0x2 a_size = 0x3 a_param = 0x0 a_source = 0x93 a_opcode = Get a_user = 0x2631c d_data = 0xa8587116 d_size = 0x1 d_param = 0x0 d_source = 0x6b d_opcode = AccessAckData d_error = 0 d_user = 1001100111111 d_sink = 0 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4851824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---