OTBN Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: `5c5f5a8`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	69.028us	1	1	100.00
V1	single_binary	otbn_single	7.000s	20.990us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	104.874us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	35.299us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	72.116us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	33.165us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	6.000s	108.423us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	35.299us	1	1	100.00
		otbn_csr_aliasing	6.000s	33.165us	1	1	100.00
V1	mem_walk	otbn_mem_walk	19.000s	951.022us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	20.000s	541.482us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	20.000s	300.783us	1	1	100.00
V2	multi_error	otbn_multi_err	46.000s	164.563us	1	1	100.00
V2	back_to_back	otbn_multi	1.033m	359.240us	1	1	100.00
V2	stress_all	otbn_stress_all	1.467m	998.832us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	74.700us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	6.000s	27.031us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	11.000s	84.313us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	20.642us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	32.945us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	29.001us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	29.001us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	104.874us	1	1	100.00
		otbn_csr_rw	6.000s	35.299us	1	1	100.00
		otbn_csr_aliasing	6.000s	33.165us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	26.226us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	104.874us	1	1	100.00
		otbn_csr_rw	6.000s	35.299us	1	1	100.00
		otbn_csr_aliasing	6.000s	33.165us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	26.226us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	13.000s	141.917us	1	1	100.00
		otbn_dmem_err	8.000s	59.044us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	424.075us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	215.071us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	35.567us	1	1	100.00
		otbn_urnd_err	7.000s	29.079us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	10.367us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	13.650us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	28.572us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	13.000s	116.869us	0	1	0.00
		otbn_tl_intg_err	21.000s	116.709us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	16.000s	191.737us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	69.028us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	59.044us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	141.917us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	21.000s	116.709us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	74.700us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	141.917us	1	1	100.00
		otbn_dmem_err	8.000s	59.044us	1	1	100.00
		otbn_zero_state_err_urnd	6.000s	27.031us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	10.367us	1	1	100.00
		otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	7.000s	20.990us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	141.917us	1	1	100.00
		otbn_dmem_err	8.000s	59.044us	1	1	100.00
		otbn_zero_state_err_urnd	6.000s	27.031us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	10.367us	1	1	100.00
		otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	74.700us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	141.917us	1	1	100.00
		otbn_dmem_err	8.000s	59.044us	1	1	100.00
		otbn_zero_state_err_urnd	6.000s	27.031us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	10.367us	1	1	100.00
		otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	7.000s	20.990us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	32.449us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	66.158us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	10.000s	18.587us	0	1	0.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	10.000s	18.587us	0	1	0.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	18.369us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	55.859us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	32.458us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	32.458us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	10.261us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	7.000s	20.990us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	7.000s	20.990us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	7.000s	20.990us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.033m	359.240us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	7.000s	20.990us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	7.000s	20.990us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	31.799us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	7.000s	20.990us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	13.000s	116.869us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.667m	599.414us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.14406068537800148070183549405791464242385555636209542449038719072371872730445
    Line 363, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 599414101 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 599414101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:
- Test otbn_rnd_sec_cm has 1 failures.
  - 0.otbn_rnd_sec_cm.33863564469808311829370888985830957640536649723131303055900540237224535676888
    Line 101, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest/run.log
```
  UVM_FATAL @  18586894 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  18586894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.62837057332611564229110908990516875278454334342499637945709649842043753295678
Line 122, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 116868628 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 116868628 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 116868628 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 116868628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---