ROM_CTRL/32KB Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.420s 181.017us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.120s 540.434us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.650s 215.492us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.970s 170.643us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.420s 427.951us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.490s 136.161us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.650s 215.492us 1 1 100.00
rom_ctrl_csr_aliasing 4.420s 427.951us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.420s 1.281ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.270s 169.773us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.220s 313.356us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 12.030s 875.121us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.580s 1.086ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.370s 299.049us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.160s 182.871us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.160s 182.871us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.120s 540.434us 1 1 100.00
rom_ctrl_csr_rw 4.650s 215.492us 1 1 100.00
rom_ctrl_csr_aliasing 4.420s 427.951us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.480s 605.786us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.120s 540.434us 1 1 100.00
rom_ctrl_csr_rw 4.650s 215.492us 1 1 100.00
rom_ctrl_csr_aliasing 4.420s 427.951us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.480s 605.786us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 12.370s 773.983us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.561m 1.145ms 1 1 100.00
rom_ctrl_tl_intg_err 21.830s 369.707us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.561m 1.145ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.561m 1.145ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.561m 1.145ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.561m 1.145ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.420s 181.017us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.420s 181.017us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.420s 181.017us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.830s 369.707us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.580s 1.086ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 48.080s 1.380ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 12.370s 773.983us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.561m 1.145ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.708m 35.023ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00