ROM_CTRL/64KB Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.710s 317.359us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.400s 1.037ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.640s 1.117ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.910s 210.843us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.930s 674.828us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.800s 225.337us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.640s 1.117ms 1 1 100.00
rom_ctrl_csr_aliasing 5.930s 674.828us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.440s 298.282us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.690s 1.010ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.670s 4.312ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.740s 3.257ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 18.390s 2.107ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.880s 363.641us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.480s 729.050us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.480s 729.050us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.400s 1.037ms 1 1 100.00
rom_ctrl_csr_rw 6.640s 1.117ms 1 1 100.00
rom_ctrl_csr_aliasing 5.930s 674.828us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.630s 865.727us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.400s 1.037ms 1 1 100.00
rom_ctrl_csr_rw 6.640s 1.117ms 1 1 100.00
rom_ctrl_csr_aliasing 5.930s 674.828us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.630s 865.727us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 36.580s 5.872ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.566m 1.758ms 1 1 100.00
rom_ctrl_tl_intg_err 1.240m 1.325ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.566m 1.758ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.566m 1.758ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.566m 1.758ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.566m 1.758ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.710s 317.359us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.710s 317.359us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.710s 317.359us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.240m 1.325ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
rom_ctrl_kmac_err_chk 18.390s 2.107ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.146m 7.342ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 36.580s 5.872ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.566m 1.758ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.196m 13.317ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00