RV_TIMER Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.610s	14.252us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.730s	17.262us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.510s	12.871us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.370s	103.661us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.500s	13.268us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.480s	23.927us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.510s	12.871us	1	1	100.00
		rv_timer_csr_aliasing	1.500s	13.268us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.890s	1.050ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.960s	4.135ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	13.740s	33.758ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	13.740s	33.758ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.310s	1.600ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.350s	44.900us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.630s	52.915us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.200s	38.085us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.200s	38.085us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.730s	17.262us	1	1	100.00
		rv_timer_csr_rw	1.510s	12.871us	1	1	100.00
		rv_timer_csr_aliasing	1.500s	13.268us	1	1	100.00
		rv_timer_same_csr_outstanding	1.470s	41.007us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.730s	17.262us	1	1	100.00
		rv_timer_csr_rw	1.510s	12.871us	1	1	100.00
		rv_timer_csr_aliasing	1.500s	13.268us	1	1	100.00
		rv_timer_same_csr_outstanding	1.470s	41.007us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.720s	680.411us	1	1	100.00
		rv_timer_tl_intg_err	1.630s	98.082us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.630s	98.082us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	55.180s	7.470ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.470s	34.163us	1	1	100.00
		rv_timer_max	1.430s	24.094us	1	1	100.00
		TOTAL			19	19	100.00