SPI_DEVICE/1R1W Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.162m	8.361ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.810s	27.752us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.080s	66.088us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.230s	1.831ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.130s	958.542us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.710s	42.744us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.080s	66.088us	1	1	100.00
		spi_device_csr_aliasing	17.130s	958.542us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.590s	36.411us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.150s	21.371us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.680s	51.976us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.600s	1.482us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.770s	3.457us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.580s	102.550us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.580s	102.550us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.840s	40.232us	1	1	100.00
		spi_device_tpm_sts_read	1.440s	52.263us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	25.800s	14.411ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.000s	857.712us	1	1	100.00
		spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	23.110s	72.788ms	1	1	100.00
		spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	23.110s	72.788ms	1	1	100.00
		spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.950s	210.954us	1	1	100.00
		spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.950s	210.954us	1	1	100.00
		spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.950s	210.954us	1	1	100.00
		spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.950s	210.954us	1	1	100.00
		spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.950s	210.954us	1	1	100.00
		spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.500s	141.730us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	23.080s	18.456ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	23.080s	18.456ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	23.080s	18.456ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.470s	228.779us	1	1	100.00
		spi_device_read_buffer_direct	4.200s	319.840us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	23.080s	18.456ms	1	1	100.00
		spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.823m	48.002ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.500s	345.431us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.500s	345.431us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.162m	8.361ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.127m	7.369ms	1	1	100.00
V2	stress_all	spi_device_stress_all	5.235m	54.568ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.500s	35.724us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.660s	40.586us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.780s	41.510us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.780s	41.510us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.810s	27.752us	1	1	100.00
		spi_device_csr_rw	2.080s	66.088us	1	1	100.00
		spi_device_csr_aliasing	17.130s	958.542us	1	1	100.00
		spi_device_same_csr_outstanding	2.200s	28.574us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.810s	27.752us	1	1	100.00
		spi_device_csr_rw	2.080s	66.088us	1	1	100.00
		spi_device_csr_aliasing	17.130s	958.542us	1	1	100.00
		spi_device_same_csr_outstanding	2.200s	28.574us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.850s	232.200us	1	1	100.00
		spi_device_tl_intg_err	16.720s	1.012ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.720s	1.012ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.710s	111.721us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.100029054699789117783132730772008214178152199207674266433426962605068568182118
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1169282 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[110])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1169282 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1169282 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1006])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.76802133615052571248404960187931273494008452522885290953830053634485349774027
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    890603 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf63e54 [111101100011111001010100] vs 0x0 [0])
        UVM_ERROR @    897603 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x440a45 [10001000000101001000101] vs 0x0 [0])
        UVM_ERROR @    968603 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ec3f3 [1111101100001111110011] vs 0x0 [0])
        UVM_ERROR @   1051603 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8fd093 [100011111101000010010011] vs 0x0 [0])
        UVM_ERROR @   1073603 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc181fc [110000011000000111111100] vs 0x0 [0])