SPI_HOST Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.017m	17.504ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	44.357us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	51.620us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	145.637us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	25.642us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	95.004us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	51.620us	1	1	100.00
		spi_host_csr_aliasing	4.000s	25.642us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	17.414us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	41.444us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	12.000s	47.616us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	9.000s	135.498us	1	1	100.00
		spi_host_error_cmd	9.000s	63.108us	1	1	100.00
		spi_host_event	16.000s	1.671ms	1	1	100.00
V2	clock_rate	spi_host_speed	16.000s	118.200us	1	1	100.00
V2	speed	spi_host_speed	16.000s	118.200us	1	1	100.00
V2	chip_select_timing	spi_host_speed	16.000s	118.200us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	22.000s	794.859us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	100.399us	1	1	100.00
V2	cpol_cpha	spi_host_speed	16.000s	118.200us	1	1	100.00
V2	full_cycle	spi_host_speed	16.000s	118.200us	1	1	100.00
V2	duplex	spi_host_smoke	1.017m	17.504ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.017m	17.504ms	1	1	100.00
V2	stress_all	spi_host_stress_all	31.000s	4.831ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	1.076ms	1	1	100.00
V2	stall	spi_host_status_stall	12.000s	633.901us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	33.815us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	9.000s	135.498us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	39.801us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	29.177us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	196.125us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	196.125us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	44.357us	1	1	100.00
		spi_host_csr_rw	3.000s	51.620us	1	1	100.00
		spi_host_csr_aliasing	4.000s	25.642us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	30.982us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	44.357us	1	1	100.00
		spi_host_csr_rw	3.000s	51.620us	1	1	100.00
		spi_host_csr_aliasing	4.000s	25.642us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	30.982us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	84.594us	1	1	100.00
		spi_host_sec_cm	5.000s	76.409us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	84.594us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.567m	14.980ms	1	1	100.00
		TOTAL			26	26	100.00