SRAM_CTRL/MAIN Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	22.510s	4.182ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.690s	50.255us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.620s	71.585us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.800s	771.195us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.650s	95.683us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.720s	1.459ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.620s	71.585us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	95.683us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.956m	98.824ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	52.580s	3.021ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.074m	9.905ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.209m	11.453ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.399m	153.722ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.573m	13.358ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.149m	83.391ms	1	1	100.00
V2	executable	sram_ctrl_executable	16.498m	96.757ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	53.740s	4.914ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.072m	42.910ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	6.000s	710.558us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	6.100s	717.097us	1	1	100.00
		sram_ctrl_throughput_w_readback	4.670s	679.667us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.341m	21.082ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.100s	344.049us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	33.041m	141.255ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.920s	12.465us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.670s	38.977us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.670s	38.977us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.690s	50.255us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	71.585us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	95.683us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	16.692us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.690s	50.255us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	71.585us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	95.683us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	16.692us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	32.970s	30.828ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.600s	19.987us	0	1	0.00
		sram_ctrl_tl_intg_err	2.710s	288.942us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.600s	19.987us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.710s	288.942us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.341m	21.082ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.341m	21.082ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.620s	71.585us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	16.498m	96.757ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	16.498m	96.757ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	16.498m	96.757ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.149m	83.391ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.350s	2.640ms	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	32.970s	30.828ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.310s	2.639ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	22.510s	4.182ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	22.510s	4.182ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	16.498m	96.757ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.600s	19.987us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.149m	83.391ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.600s	19.987us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.600s	19.987us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	22.510s	4.182ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.600s	19.987us	0	1	0.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.099m	1.710ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.39076210391488810599412348771067614677296144508409728163373807178747534094263
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2638745546 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x26) != exp (0x28)
        UVM_INFO @ 2638745546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.28955817177646894409905166564853781653881002680852147496717078004808373572847
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2639529968 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2639529968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.90132232921118682506533824918721152773738483906629341031984099626943439634015
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  19987424 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  19987424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---