SRAM_CTRL/RET Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	27.590s	1.558ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.480s	32.231us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.480s	17.817us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.620s	317.751us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.540s	42.006us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.890s	121.079us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.480s	17.817us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	42.006us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.020s	189.202us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.990s	234.969us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.796m	48.769ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.273m	15.576ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.970s	1.221ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.896m	4.710ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.680s	926.407us	1	1	100.00
V2	executable	sram_ctrl_executable	2.990m	1.786ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.960s	4.236ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.023m	12.650ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	14.290s	90.716us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	36.690s	1.052ms	1	1	100.00
		sram_ctrl_throughput_w_readback	49.110s	471.517us	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.640m	10.616ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.600s	107.405us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	29.730m	11.860ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.590s	18.230us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.630s	150.712us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.630s	150.712us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.480s	32.231us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	17.817us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	42.006us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	19.499us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.480s	32.231us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	17.817us	1	1	100.00
		sram_ctrl_csr_aliasing	1.540s	42.006us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	19.499us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.020s	1.645ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.620s	1.920us	0	1	0.00
		sram_ctrl_tl_intg_err	2.160s	104.968us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.620s	1.920us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.160s	104.968us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.640m	10.616ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.640m	10.616ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.480s	17.817us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.990m	1.786ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.990m	1.786ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.990m	1.786ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.680s	926.407us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.730s	47.023us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.020s	1.645ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.820s	27.246us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	27.590s	1.558ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	27.590s	1.558ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.990m	1.786ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.620s	1.920us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.680s	926.407us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.620s	1.920us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.620s	1.920us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	27.590s	1.558ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.620s	1.920us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	54.120s	20.783ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.59866051114542253854828546454636274110184914518014148074089743830124371999769
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  27245847 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x15) != exp (0x6d)
        UVM_INFO @  27245847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.95554335109862998907370802870140376099940119264350539130703798696371231049699
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @   1920043 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @   1920043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---