UART Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.190s	798.979us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.490s	18.578us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.440s	13.061us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.500s	363.145us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.530s	16.817us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.610s	25.931us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.440s	13.061us	1	1	100.00
		uart_csr_aliasing	1.530s	16.817us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	26.450s	382.682ms	1	1	100.00
V2	parity	uart_smoke	2.190s	798.979us	1	1	100.00
		uart_tx_rx	26.450s	382.682ms	1	1	100.00
V2	parity_error	uart_intr	1.743m	71.798ms	1	1	100.00
		uart_rx_parity_err	32.550s	31.843ms	1	1	100.00
V2	watermark	uart_tx_rx	26.450s	382.682ms	1	1	100.00
		uart_intr	1.743m	71.798ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.032m	199.261ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	47.380s	545.824ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	58.420s	112.627ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.743m	71.798ms	1	1	100.00
V2	rx_break_err	uart_intr	1.743m	71.798ms	1	1	100.00
V2	rx_timeout	uart_intr	1.743m	71.798ms	1	1	100.00
V2	perf	uart_perf	1.865m	11.029ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.020s	5.880ms	1	1	100.00
V2	line_loopback	uart_loopback	4.020s	5.880ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	16.950s	15.318ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.740s	2.146ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.560s	814.207us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.910s	7.543ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.838m	124.962ms	1	1	100.00
V2	stress_all	uart_stress_all	3.623m	137.149ms	1	1	100.00
V2	alert_test	uart_alert_test	1.510s	17.749us	1	1	100.00
V2	intr_test	uart_intr_test	1.490s	15.786us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.230s	414.819us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.230s	414.819us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.490s	18.578us	1	1	100.00
		uart_csr_rw	1.440s	13.061us	1	1	100.00
		uart_csr_aliasing	1.530s	16.817us	1	1	100.00
		uart_same_csr_outstanding	1.520s	29.348us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.490s	18.578us	1	1	100.00
		uart_csr_rw	1.440s	13.061us	1	1	100.00
		uart_csr_aliasing	1.530s	16.817us	1	1	100.00
		uart_same_csr_outstanding	1.520s	29.348us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.860s	377.249us	1	1	100.00
		uart_tl_intg_err	1.800s	47.685us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.800s	47.685us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	11.330s	1.160ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00