CHIP Simulation Results

Thursday May 29 2025 17:01:18 UTC

GitHub Revision: `5c5f5a8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.037m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.037m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.146m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.357m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	59.466s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.710m	5.685ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.710m	5.685ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.710m	5.685ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	39.020s	10.380us	0	1	0.00
		chip_sw_example_manufacturer	2.672m		0	1	0.00
		chip_sw_example_concurrency	3.858m	5.143ms	1	1	100.00
		chip_sw_uart_smoketest_signed	33.734s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	13.940s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	15.810s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	15.810s		0	1	0.00
V1	xbar_smoke	xbar_smoke	20.170s	61.752us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.566m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.065m	7.676ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.682m	6.282ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.295m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	10.749s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.074m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	50.072s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.280s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.280s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.950m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.121m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.361m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.361m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.176m	4.908ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.679m	3.464ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.560m	13.022ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.872s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.468s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.639m	24.670ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.524m	6.730ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.410m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.410m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.635s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.743m	3.797ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.743m	3.797ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.815m	18.017ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.978m	4.419ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.866m	5.534ms	1	1	100.00
		chip_sw_aes_idle	4.248m	5.684ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.417m	4.363ms	1	1	100.00
		chip_sw_kmac_idle	4.611m	5.434ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.493m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.051m	12.023ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.179m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.251m	12.016ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.448s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.129s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.837s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.700s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.437s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.901s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.242s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.448s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.129s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.837s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.700s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.437s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.901s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.242s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.948s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.950s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	51.550s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.790s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.004m	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.207s		0	1	0.00
		chip_sw_clkmgr_jitter	3.538m	4.268ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.540m	3.438ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.488s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	48.430s	10.120us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	51.530s	10.260us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	53.320s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	56.580s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	52.410s	10.220us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.350s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.291s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.644s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.056s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.985m	13.526ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.750m	10.654ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.743m	3.797ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	16.123s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.750m	10.654ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	12.653s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.309s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	25.836s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	17.567s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.796s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.985m	13.526ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.560m	13.022ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	22.658m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.157m	8.379ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.441m	7.844ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.504m	4.680ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.985m	13.526ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.834s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.011s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.985m	13.526ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.686s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.441m	7.844ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.718s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.300s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.834s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.080s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.871s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.112s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.011s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	16.158s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	33.060s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.158s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.158s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.158s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.962m	10.431ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	36.424s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	30.781s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.664s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.978s		0	1	0.00
		chip_sw_lc_ctrl_transition	16.158s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.869m	8.519ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.308m	15.105ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.003s		0	1	0.00
		chip_prim_tl_access	6.761m	12.274ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.448s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.129s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.837s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.700s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.437s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.901s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.242s		0	1	0.00
		chip_rv_dm_lc_disabled	12.639m	24.670ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.696m	3.854ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	47.950s	10.220us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.415m	4.732ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.248m	5.684ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.938m	3.507ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	51.550s	10.240us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.417m	4.363ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.908m	4.727ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.719m	4.854ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.004m	10.140us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.869m	8.519ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.158s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	46.800s	10.300us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.619m	5.261ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.611m	5.434ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.419s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.419s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.042s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.341m	4.413ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.867s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.869m	8.519ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.790s	10.120us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.856s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.948s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.866m	5.534ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.866m	5.534ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.866m	5.534ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	9.003m	6.172ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.308m	15.105ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.308m	15.105ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.725m	8.461ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.207s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.003s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.985m	13.526ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.361m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.158s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	9.003m	6.172ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.869m	8.519ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.725m	8.461ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.956m	3.113ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	9.003m	6.172ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.869m	8.519ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.725m	8.461ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.956m	3.113ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.158s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.011s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	33.060s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	36.424s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	30.781s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.664s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.978s		0	1	0.00
		chip_sw_lc_ctrl_transition	16.158s		0	1	0.00
		chip_prim_tl_access	6.761m	12.274ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.761m	12.274ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.582s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	20.106s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.291s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.948s		0	1	0.00
		chip_sw_aes_enc_jitter_en	47.950s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	51.550s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.790s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.004m	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.207s		0	1	0.00
		chip_sw_clkmgr_jitter	3.538m	4.268ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	6.901m	8.876ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	6.901m	8.876ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.985m	5.160ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.603m	5.207ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.554m	5.452ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.611m	5.801ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.346m	4.093ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.915m	4.722ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.956m	3.113ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	22.658m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	22.658m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.668m	3.971ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.354m	5.185ms	1	1	100.00
		chip_sw_clkmgr_smoketest	4.159m	4.939ms	1	1	100.00
		chip_sw_csrng_smoketest	3.295m	4.739ms	1	1	100.00
		chip_sw_gpio_smoketest	3.809m	4.120ms	1	1	100.00
		chip_sw_hmac_smoketest	4.111m	6.022ms	1	1	100.00
		chip_sw_kmac_smoketest	4.719m	5.315ms	1	1	100.00
		chip_sw_otbn_smoketest	5.267m	4.679ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.397m	5.823ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.458m	3.891ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.158m	6.172ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.420m	3.285ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.187m	3.967ms	1	1	100.00
		chip_sw_uart_smoketest	3.622m	3.685ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	41.619s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	33.734s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.566m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.795s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.432m	3.918ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.175m	6.096ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.134m	4.983ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.437m	3.362ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	59.558s		0	1	0.00
		chip_rv_dm_lc_disabled	12.639m	24.670ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.002s		0	1	0.00
		chip_sw_lc_walkthrough_prod	18.055s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	16.616s		0	1	0.00
		chip_sw_lc_walkthrough_rma	14.490s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	59.558s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	20.491s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.480s		0	1	0.00
		rom_volatile_raw_unlock	10.730s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.597s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.160m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.055m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.263m	3.833ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.263m	3.833ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	15.810s		0	1	0.00
		chip_same_csr_outstanding	13.490s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	15.810s		0	1	0.00
		chip_same_csr_outstanding	13.490s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.087m	178.230us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	11.920s	12.644us	1	1	100.00
		xbar_smoke_large_delays	4.292m	2.242ms	1	1	100.00
		xbar_smoke_slow_rsp	5.477m	1.946ms	1	1	100.00
		xbar_random_zero_delays	1.319m	71.271us	1	1	100.00
		xbar_random_large_delays	3.947m	2.028ms	1	1	100.00
		xbar_random_slow_rsp	33.127m	12.924ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.682m	204.827us	1	1	100.00
		xbar_error_and_unmapped_addr	39.970s	29.965us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	15.210s	18.608us	1	1	100.00
		xbar_error_and_unmapped_addr	39.970s	29.965us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.451m	533.254us	1	1	100.00
		xbar_access_same_device_slow_rsp	25.471m	9.636ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.815m	348.759us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.874m	157.532us	1	1	100.00
		xbar_stress_all_with_error	4.477m	326.905us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	29.401m	1.182ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.419m	101.206us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.379s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.591s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.744s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.679s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.496s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.323s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.458s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.806s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.170s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.006s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.414s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.936s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.807s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.655s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.333s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.721s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.358s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.763s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.878s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.490s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.053s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.667s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.614s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.296s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.567s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.128s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.218s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.092s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.119s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.626s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.271s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.785s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.223s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.990s		0	1	0.00
		rom_e2e_asm_init_dev	12.376s		0	1	0.00
		rom_e2e_asm_init_prod	11.240s		0	1	0.00
		rom_e2e_asm_init_prod_end	10.845s		0	1	0.00
		rom_e2e_asm_init_rma	11.338s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.971s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.895s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.818s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.937s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.013m	4.226ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.609m	5.781ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.906s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.134s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.756s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.856s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.985m	13.526ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.088s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.255m	14.438ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.718s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.458s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.906s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.134s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.756s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.061s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.572s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.233s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	55.917s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.440m	13.825ms	1	1	100.00
		chip_plic_all_irqs_0	9.238m	5.652ms	1	1	100.00
		chip_plic_all_irqs_10	9.763m	8.485ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.581m	5.932ms	1	1	100.00
		chip_sw_dma_abort	4.381m	5.594ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.285s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.911s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.184s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.378s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.836s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.176s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.973s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.355s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.524s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.524s		0	1	0.00
		chip_sw_mbx_smoketest	4.744m	5.094ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.31725352743661392833520683916653572844102624115662092293612732429895596655932
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (22ed33)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 142.894s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.15143018058535804439926363994951633754570993924619822516269129008126044356340
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (9c2727)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 130.297s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.53240325433100857115574576489452706648863017553580506838848088008248242478256
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (685cdd)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 105.222s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.42404819558436316116191874570664549914883105000980595715707380870678819733422
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (d9ecda)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 116.349s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.89150997198382133196332439354337220576477206961321908860697979698622401378455
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b100c8)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 112.304s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.37365690642820685645544223950049759436929247720113279216593294752842240362431
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.90583003938156343344770921285867971717604629151549095355410660049619592726382
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.94076464340497747972657185439078901803190111924224493192114795633695631692011
    Line 411, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.96761936833679005948018942491484842089876383487778856623996145528013254122170
    Line 410, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.83495869386349809713252361201438013757865857729397567138034263838758473005187
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.105612487206012503058334946260342959214783228795775737615117382264274280440431
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12015.458935 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.458935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.59778285605119568276550698811862491119140020000463680345770861623469478162809
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12022.535836 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.535836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.66992868011716550295106487597279683609707682632352651467417675348452627477655
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12014.892857 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.892857 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.30852060596991778529836727634100249815677318448268543745020531580504047694858
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12016.295059 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.295059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.93839563301674333772751806767875006005043111684430625392584152151192681286867
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.33042026395613177740086680690078411686352334249158061794671666337241922273780
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.7440338390918773171041976299115241917104217086850306113028831935616257936861
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.99714533078016341325665234762236199605469913444234477497360849352789448381230
Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.107091 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.107091 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.18112241467689133505734223959887515100082093774882203326906044881040948600161
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.604377 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.604377 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.114816607583122745972093565189238293577799867992489258454548378253891517510129
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18017.441153 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.441153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.82703927712649002303901373785273774709238410997433046163410183918117983039823
Line 470, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8519.201610 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (65460871950335867099668072733585903398937951114075951788239523078328304551968 [0x90b98a60acebed5393b784617d832acd4d038d7bd5e9f56e4ce95561f6284820] vs 36046128088239069793599028717700103065931502299805892457743521449741343646863 [0x4fb162b022358ff692268162906ce0ddf3accaa05528ec7708a964d36bdde48f])
  UVM_INFO @ 8519.201610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.20281805066122115978961051038231645594918782065826304535464653340658196207590
Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 10430.884280 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (101135918448747805409607348913420307924971496563232566385621466909242102620657 [0xdf98e6bba7b919347fc70b9fc9f03789ab732d5f9435f7d6617db1ab3013a1f1] vs 29680113825156490400745595165590149120635008069039630001504028537156017502806 [0x419e595f88a2ad0e84ffd478c5b63f3804b8ab428fff1fe45ae52110a0d2ba56])
  UVM_INFO @ 10430.884280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.83604650594093622019480318288571975845744467235425310012900299733578225048755
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4907.919412 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h5e41ab9f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h0  a_user: 'h26940  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4907.919412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.61341951052099365795973642725494356866326889961699282591478087147813759773452
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3463.765317 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h3df206c8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h26906  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3463.765317 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.114255857128642186304500268115442149252088872625704612953359665586096852474151
    Line 579, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.69721379986423839613274121909056799047521486190493594503183105589667912798652
    Line 494, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 6282.229706 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 6282.229706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.41029253748711099400372041446198647903294389887622587531281146228621717940044
    Line 688, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 7843.578858 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 7843.578858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.52032070512837335071746765973967145771312433323227553889094738682807650824672
    Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5160.119124 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5160.119124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.75967876342765898963980110443399051636584353279275991240607285860458983519117
    Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5207.482646 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5207.482646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.65337684270734980220299340785477136896695081302364118730402003025957204094979
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3796.707960 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3796.707960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.36548218413396820934867826548463486673935381450950059181278313194793443523606
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5800.853112 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5800.853112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.113808467429157707948123930139939655242867098933189635181962376704946628119459
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35904) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.107004863058476860497763039497417120838712826878036990340145633573957387302737
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3832.689496 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35904) { a_addr: 'h2212  a_data: 'h40a992b9  a_mask: 'h0  a_size: 'h0  a_param: 'h0  a_source: 'hdd  a_opcode: 'h4  a_user: 'h241ba  d_param: 'h0  d_source: 'hdd  d_data: 'h0  d_size: 'h0  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h4aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3832.689496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.3187210015909396127917581028590219829466068844655674300965115865528825463934
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13021.504744 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13021.504744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.42830467915709628495517194111829936519484840860709163544700988796570206275358
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.25266841965225571166812640348847674224422825288538558479345880149535509100
    Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5593.985900 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5593.985900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```