DMA Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	9.000s	1.420ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	329.940us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	395.044us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	18.418us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	56.978us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	8.000s	305.373us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	1.108ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	74.482us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	56.978us	1	1	100.00
		dma_csr_aliasing	7.000s	1.108ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	40.000s	10.804ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	5.500m	57.224ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	8.317m	40.771ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	41.483m	1.042s	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	5.500m	57.224ms	1	1	100.00
V2	dma_abort	dma_abort	12.000s	558.929us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.500m	6.213ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	14.861us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	125.190us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	125.190us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	18.418us	1	1	100.00
		dma_csr_rw	4.000s	56.978us	1	1	100.00
		dma_csr_aliasing	7.000s	1.108ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	127.467us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	18.418us	1	1	100.00
		dma_csr_rw	4.000s	56.978us	1	1	100.00
		dma_csr_aliasing	7.000s	1.108ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	127.467us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	19.000s	130.471us	1	1	100.00
		dma_generic_stress	41.483m	1.042s	1	1	100.00
		dma_handshake_stress	5.500m	57.224ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	316.133us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.133m	6.113ms	1	1	100.00
		dma_longer_transfer	7.000s	770.399us	1	1	100.00
		TOTAL			21	21	100.00