EDN Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.030s	30.395us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.780s	20.079us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.790s	15.856us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.440s	725.935us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.290s	183.428us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.270s	21.053us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.790s	15.856us	1	1	100.00
		edn_csr_aliasing	2.290s	183.428us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.550s	56.056us	1	1	100.00
V2	csrng_commands	edn_genbits	2.550s	56.056us	1	1	100.00
V2	genbits	edn_genbits	2.550s	56.056us	1	1	100.00
V2	interrupts	edn_intr	1.830s	62.154us	1	1	100.00
V2	alerts	edn_alert	1.880s	45.710us	1	1	100.00
V2	errs	edn_err	1.890s	41.267us	1	1	100.00
V2	disable	edn_disable	2.080s	22.784us	1	1	100.00
		edn_disable_auto_req_mode	2.130s	219.689us	1	1	100.00
V2	stress_all	edn_stress_all	3.850s	457.291us	1	1	100.00
V2	intr_test	edn_intr_test	1.610s	44.931us	1	1	100.00
V2	alert_test	edn_alert_test	1.660s	46.716us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.090s	49.490us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.090s	49.490us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.780s	20.079us	1	1	100.00
		edn_csr_rw	1.790s	15.856us	1	1	100.00
		edn_csr_aliasing	2.290s	183.428us	1	1	100.00
		edn_same_csr_outstanding	1.730s	44.064us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.780s	20.079us	1	1	100.00
		edn_csr_rw	1.790s	15.856us	1	1	100.00
		edn_csr_aliasing	2.290s	183.428us	1	1	100.00
		edn_same_csr_outstanding	1.730s	44.064us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	7.310s	493.686us	1	1	100.00
		edn_tl_intg_err	2.990s	124.023us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.740s	22.440us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.880s	45.710us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.310s	493.686us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.310s	493.686us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.310s	493.686us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.310s	493.686us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.880s	45.710us	1	1	100.00
		edn_sec_cm	7.310s	493.686us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.880s	45.710us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.990s	124.023us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.297m	20.180ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00