HMAC Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.130s 53.013us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.660s 19.100us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.600s 40.437us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.710s 581.845us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.680s 210.531us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.800s 97.627us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.600s 40.437us 1 1 100.00
hmac_csr_aliasing 4.680s 210.531us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 59.530s 1.589ms 1 1 100.00
V2 back_pressure hmac_back_pressure 16.340s 4.011ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.173m 13.043ms 1 1 100.00
hmac_test_sha384_vectors 19.490s 447.813us 1 1 100.00
hmac_test_sha512_vectors 6.482m 25.319ms 1 1 100.00
hmac_test_hmac256_vectors 9.110s 897.853us 1 1 100.00
hmac_test_hmac384_vectors 10.410s 648.769us 1 1 100.00
hmac_test_hmac512_vectors 8.840s 950.665us 1 1 100.00
V2 burst_wr hmac_burst_wr 5.960s 1.324ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.669m 12.874ms 1 1 100.00
V2 error hmac_error 35.060s 3.665ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 9.110s 668.805us 1 1 100.00
V2 save_and_restore hmac_smoke 2.130s 53.013us 1 1 100.00
hmac_long_msg 59.530s 1.589ms 1 1 100.00
hmac_back_pressure 16.340s 4.011ms 1 1 100.00
hmac_datapath_stress 1.669m 12.874ms 1 1 100.00
hmac_burst_wr 5.960s 1.324ms 1 1 100.00
hmac_stress_all 19.172m 86.814ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.130s 53.013us 1 1 100.00
hmac_long_msg 59.530s 1.589ms 1 1 100.00
hmac_back_pressure 16.340s 4.011ms 1 1 100.00
hmac_datapath_stress 1.669m 12.874ms 1 1 100.00
hmac_wipe_secret 9.110s 668.805us 1 1 100.00
hmac_test_sha256_vectors 3.173m 13.043ms 1 1 100.00
hmac_test_sha384_vectors 19.490s 447.813us 1 1 100.00
hmac_test_sha512_vectors 6.482m 25.319ms 1 1 100.00
hmac_test_hmac256_vectors 9.110s 897.853us 1 1 100.00
hmac_test_hmac384_vectors 10.410s 648.769us 1 1 100.00
hmac_test_hmac512_vectors 8.840s 950.665us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.130s 53.013us 1 1 100.00
hmac_long_msg 59.530s 1.589ms 1 1 100.00
hmac_back_pressure 16.340s 4.011ms 1 1 100.00
hmac_datapath_stress 1.669m 12.874ms 1 1 100.00
hmac_burst_wr 5.960s 1.324ms 1 1 100.00
hmac_error 35.060s 3.665ms 1 1 100.00
hmac_wipe_secret 9.110s 668.805us 1 1 100.00
hmac_test_sha256_vectors 3.173m 13.043ms 1 1 100.00
hmac_test_sha384_vectors 19.490s 447.813us 1 1 100.00
hmac_test_sha512_vectors 6.482m 25.319ms 1 1 100.00
hmac_test_hmac256_vectors 9.110s 897.853us 1 1 100.00
hmac_test_hmac384_vectors 10.410s 648.769us 1 1 100.00
hmac_test_hmac512_vectors 8.840s 950.665us 1 1 100.00
hmac_stress_all 19.172m 86.814ms 1 1 100.00
V2 stress_all hmac_stress_all 19.172m 86.814ms 1 1 100.00
V2 alert_test hmac_alert_test 1.390s 227.659us 1 1 100.00
V2 intr_test hmac_intr_test 1.560s 117.012us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.110s 119.785us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.110s 119.785us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.660s 19.100us 1 1 100.00
hmac_csr_rw 1.600s 40.437us 1 1 100.00
hmac_csr_aliasing 4.680s 210.531us 1 1 100.00
hmac_same_csr_outstanding 2.220s 112.100us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.660s 19.100us 1 1 100.00
hmac_csr_rw 1.600s 40.437us 1 1 100.00
hmac_csr_aliasing 4.680s 210.531us 1 1 100.00
hmac_same_csr_outstanding 2.220s 112.100us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.680s 95.384us 1 1 100.00
hmac_tl_intg_err 2.390s 333.661us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.390s 333.661us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.130s 53.013us 1 1 100.00
V3 stress_reset hmac_stress_reset 6.620s 579.641us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 39.130s 1.111ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.760s 23.711us 1 1 100.00
TOTAL 28 28 100.00