I2C Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	56.310s	1.826ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.490s	938.016us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.020s	26.459us	1	1	100.00
V1	csr_rw	i2c_csr_rw	2.120s	29.352us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.950s	500.542us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.860s	441.371us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.080s	135.303us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.120s	29.352us	1	1	100.00
		i2c_csr_aliasing	2.860s	441.371us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.360s	129.561us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	6.176m	58.819ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	7.080s	553.065us	1	1	100.00
V2	host_override	i2c_host_override	1.650s	126.228us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.160m	19.187ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	36.960s	2.176ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.900s	429.319us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.290s	733.553us	1	1	100.00
		i2c_host_fifo_reset_rx	7.210s	316.257us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.255m	3.534ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	22.100s	2.748ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.600s	23.924us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.870s	2.266ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	28.040s	63.114ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.380s	3.493ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	5.510s	1.126ms	1	1	100.00
		i2c_target_intr_smoke	5.370s	1.148ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.440s	708.725us	1	1	100.00
		i2c_target_fifo_reset_tx	1.760s	1.105ms	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.798m	55.799ms	1	1	100.00
		i2c_target_stress_rd	5.510s	1.126ms	1	1	100.00
		i2c_target_intr_stress_wr	1.139m	30.080ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.990s	1.244ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.260s	795.347us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.370s	1.041ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.810s	841.467us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.800s	443.273us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.030s	309.752us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	7.080s	553.065us	1	1	100.00
		i2c_host_perf_precise	2.690s	462.653us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	22.100s	2.748ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	6.450s	486.232us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.900s	752.410us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.940s	1.104ms	1	1	100.00
		i2c_target_nack_txstretch	2.160s	1.663ms	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	12.670s	1.976ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.680s	531.560us	1	1	100.00
V2	alert_test	i2c_alert_test	1.810s	28.135us	1	1	100.00
V2	intr_test	i2c_intr_test	1.800s	41.904us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.430s	342.487us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.430s	342.487us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.020s	26.459us	1	1	100.00
		i2c_csr_rw	2.120s	29.352us	1	1	100.00
		i2c_csr_aliasing	2.860s	441.371us	1	1	100.00
		i2c_same_csr_outstanding	2.060s	49.857us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.020s	26.459us	1	1	100.00
		i2c_csr_rw	2.120s	29.352us	1	1	100.00
		i2c_csr_aliasing	2.860s	441.371us	1	1	100.00
		i2c_same_csr_outstanding	2.060s	49.857us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.390s	508.454us	1	1	100.00
		i2c_sec_cm	1.700s	97.267us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.390s	508.454us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	3.230s	270.998us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.020s	329.260us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.140s	1.901ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.59108855699614322738537226296480083432589747385902029275951161884449994614573
      Line 117, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 270998288 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 270998288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.4819815037415058755719631131161482491923763267683099459411369924770672753904
      Line 98, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1900921524 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1900921524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.50835059964077445806066593044897607468778171124553388345138538789159483281164
      Line 116, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 58819362655 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @664706
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.92082018886958339104677145652692142174462747973408238585870383854549849856719
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 329259780 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 216 [0xd8])
        UVM_INFO @ 329259780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.89602345238116909036345558489713648015353110123137213796856544520427721095413
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  23924011 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.32633547871585351360239024376032604458325996751896079687737002292813779285750
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 1663151577 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 1663151577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---