KEYMGR Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.600s	1.109ms	1	1	100.00
V1	random	keymgr_random	5.160s	469.922us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.400s	88.660us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.290s	17.764us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.630s	1.789ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	11.220s	363.371us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.210s	88.228us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.290s	17.764us	1	1	100.00
		keymgr_csr_aliasing	11.220s	363.371us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.280s	72.845us	1	1	100.00
V2	sideload	keymgr_sideload	30.560s	1.306ms	1	1	100.00
		keymgr_sideload_kmac	3.280s	184.027us	1	1	100.00
		keymgr_sideload_aes	2.240s	85.872us	1	1	100.00
		keymgr_sideload_otbn	5.440s	786.475us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.570s	380.683us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.670s	373.522us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	5.180s	163.946us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.660s	269.487us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.520s	1.303ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.420s	60.478us	1	1	100.00
V2	stress_all	keymgr_stress_all	28.350s	2.828ms	1	1	100.00
V2	intr_test	keymgr_intr_test	2.170s	11.696us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.640s	39.325us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.660s	55.670us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.660s	55.670us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.400s	88.660us	1	1	100.00
		keymgr_csr_rw	2.290s	17.764us	1	1	100.00
		keymgr_csr_aliasing	11.220s	363.371us	1	1	100.00
		keymgr_same_csr_outstanding	3.020s	149.308us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.400s	88.660us	1	1	100.00
		keymgr_csr_rw	2.290s	17.764us	1	1	100.00
		keymgr_csr_aliasing	11.220s	363.371us	1	1	100.00
		keymgr_same_csr_outstanding	3.020s	149.308us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
		keymgr_tl_intg_err	4.990s	111.989us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.940s	855.660us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.940s	855.660us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.940s	855.660us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.940s	855.660us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	2.040s	30.106us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.990s	111.989us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.940s	855.660us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.280s	72.845us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.160s	469.922us	1	1	100.00
		keymgr_csr_rw	2.290s	17.764us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.160s	469.922us	1	1	100.00
		keymgr_csr_rw	2.290s	17.764us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.160s	469.922us	1	1	100.00
		keymgr_csr_rw	2.290s	17.764us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.670s	373.522us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.520s	1.303ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.520s	1.303ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.160s	469.922us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.060s	51.532us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.580s	231.771us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.670s	373.522us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.580s	231.771us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.580s	231.771us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.580s	231.771us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.030s	552.701us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.580s	231.771us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	15.220s	854.421us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.61207492634117438170497745213688312640479469583274061886107410523189155780252
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
        UVM_ERROR @  30106419 ps: (keymgr_csr_assert_fpv.sv:469) [ASSERT FAILED] attest_sw_binding_7_rd_A
        UVM_INFO @  30106419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---